82801BA Datasheet, PDF (126/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.10.2
5.10.3
5.10.4
5.10.5
Interrupts
The real-time clock interrupt is internally routed within the ICH2 both to the I/O APIC and the
8259. It is mapped to interrupt vector 8. This interrupt does not leave the ICH2, nor is it shared with
any other interrupt. IRQ8# from the SERIRQ stream is ignored.
Lockable RAM Ranges
The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the
configuration space. If the locking bits are set, the corresponding range in the RAM are not
readable or writable. A write cycle to those locations has no effect. A read cycle to those locations
does not return the location’s actual value (may be all 0s or all 1s).
Once a range is locked, the range can be unlocked only by a hard reset, which invokes BIOS and
allows it to relock the RAM range.
Century Rollover
ICH2 detects a rollover when the Year byte (RTC I/O space, index offset 09h) transitions form
99 to 00. Upon detecting the rollover, the ICH2 sets the NEWCENTURY_STS bit
(TCOBASE + 04h, bit 7). If the system is in an S0 state, this causes an SMI#. The SMI# handler
can update registers in the RTC RAM that are associated with century value. If the system is in a
sleep state (S1–S5) when the century rollover occurs, the ICH2 also sets the NEWCENTURY_STS
bit; no SMI# is generated. When the system resumes from the sleep state, BIOS should check the
NEWCENTURY_STS bit and update the century value in the RTC RAM.
Clearing Battery-Backed RTC RAM
Clearing CMOS RAM in an ICH2-based platform can be done by using a jumper on RTCRST# or
GPI or using the SAFEMODE strap. Implementations should not attempt to clear CMOS by using
a jumper to pull VccRTC low.
Using RTCRST# to clear CMOS
A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of
the configuration bits that reside in the RTC power well. When the RTCRST# is strapped to
ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) is set and the configuration bits in the RTC
power well are set to their default state. BIOS can monitor the state of this bit and manually clear
the RTC CMOS array once the system is booted. The normal position would cause RTCRST# to be
pulled up through a weak pull-up resistor. Table 5-30 shows which bits are set to their default state
when RTCRST# is asserted.
RTCRST# should be used to reset configuration bits (and signal BIOS to clear CMOS) ONLY in a
G3 state. Additionally, RTCRST# assertion while power is on must ONLY be done to invoke the
test modes, and that it should only be asserted for the specific number of clocks to invoke the
desired test mode. Assertion for any other number of clocks may put the component into an
indeterminate state, which is not supported.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet