82801BA Datasheet, PDF (477/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Testability
Table 17-6. XOR Chain #4 (RTCRST# Asserted for 7 PCI Clocks while PWROK Active)
Pin Name
SDD13
SDD1
SDD14
SDD0
SDIOR#
SDDREQ
SDIOW#
SDD15
SDA1
SDDACK#
IRQ15
SIORDY
SDA2
SDCS3#
Ball #
Notes
A19 Top of XOR Chain
B19 2nd signal in XOR
C18
D18
D17
B18
C17
A18
D16
B17
C16
A17
B16
D15
SDA0
A16
SDCS1#
VRMPWRGD
(ICH2)
VRMPWRGD /
VGATE (ICH2-M)
GPIO18 (ICH2)
STP_PCI#
(ICH2-M)
GPIO19 (ICH2)
SLP_S1#
(ICH2-M)
GPIO20 (ICH2)
STP_CPU#
(ICH2-M)
GPIO22 (ICH2)
CPUPERF#
(ICH2-M)
GPIO23 (ICH2)
SSMUXSEL#
(ICH2-M)
A20GATE
RCIN#
CPUPWRGD
C15
B15
A15
D14
C14
B14
A14
C13
B13
A13
Pin Name
INIT#
SMI#
CPUSLP#
IGNNE#
NMI
INTR
A20M#
STPCLK#
HL7
HL5
HL6
HL4
HL8
HL10
HL_STB#
HL_STB
Ball #
Notes
C12
B12
A12
A11
B11
C11
D11
C10
A9
A8
B8
B7
C8
C7
See
Section 17.3.1.1
A7
See
Section 17.3.1.1
A6
HL9
C6
HL2
HL1
HL0
HL11
HLCOMP
OC0#
A5
B5
A4
C5
A3 Last in XOR Chain
W19
XOR Chain #4
OUTPUT
82801BA ICH2 and 82801BAM ICH2-M Datasheet
17-7