82801BA Datasheet, PDF (332/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.3.10 GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 2Ah
(ACPI GPE0_BLK + 2)
0000h
No
Bits 0–7 Resume,
Bits 8–15 RTC
Attribute:
Size:
Usage:
R/W
16-bit
ACPI
Note: This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this
register should be cleared to 0 based on a Power Button Override. The resume well bits are all
cleared by RSMRST#. The RTC sell bits are cleared by RTCRST#.
Bit
15:12
11
10
9
8
7
6
5
4
3
2
1
0
Description
Reserved.
PME# Enable (PME_EN)—R/W.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be
a wake event from the S1–S4 state or from S5 (if entered via SLP_EN, but not power button
override).
ICH2 (82801BA):
Reserved
ICH2-M (82801BAM):
BATLOW_EN — R/W.
0 = Disable.
1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the SCI_EN bit) when
it goes low. This bit does not prevent the BATLOW# signal from inhibiting the wake event.
Reserved
RI_EN—R/W. The value of this bit will be maintained through a G3 state and is not affected by a
hard reset caused by RSMRST# or a CF9h write. Assertion of RTCRST# resets this bit.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
Reserved
TCO SCI Enable (TCOSCI_EN)—R/W.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
AC97 Enable (AC97_EN)—R/W.
0 = Disable.
1 = Enables the setting of the AC97_STS to generate a wake event.
USB Controller 2 Enable (USB2_EN)—R/W.
0 = Disable.
1 = Enables the setting of the USB2_STS to generate a wake event.
USB Controller 1 Enable (USB1_EN)—R/W.
0 = Disable.
1 = Enables the setting of the USB1_STS to generate a wake event.
Thermal Pin Polarity (THRM#_POL)—R/W. This bit controls the polarity of the THRM# pin
needed to set the THRM_STS bit.
0 = Low value on the THRM# signal will set the THRM_STS bit.
1 = HIGH value on the THRM# signal will set the THRM_STS bit.
Reserved.
Thermal Signal Reporting Enable (THRM_EN)—R/W.
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the
THRM_STS bit and generate a power management event (SCI or SMI).
9-70
82801BA ICH2 and 82801BAM ICH2-M Datasheet