82801BA Datasheet, PDF (120/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.8.5.4
Registers Associated with Front-Side Bus Interrupt Delivery
Capabilities Indication
The capability to support Front-Side bus interrupt delivery will be indicated via ACPI
configuration techniques. This involves BIOS creating a data structure that gets reported to the
ACPI configuration software.
DT bit in the Boot Configuration Register
This enables the ICH2 to deliver interrupts as memory writes. This bit is ignored if the APIC mode
is not enabled.
5.8.5.5 Interrupt Message Format
ICH2 writes the message to PCI (and to the Host Controller) as a 32-bit memory write cycle. It uses
the formats shown in Table 5-26 and Table 5-27 for the address and data.
:
Table 5-26. Interrupt Message Address Format
Bit
31:20
19:12
11:4
3
2
1:0
Description
Will always be FEEh
Destination ID: This is the same as bits 63:56 of the I/O Redirection Table entry for the interrupt
associated with this message.
Reserved (will always be 0)
Redirection Hint: This bit is used by the processor host bridge to allow the interrupt message to be
redirected.
0 = The message will be delivered to the agent (processor) listed in bits 19:4.
1 = The message will be delivered to an agent with a lower interrupt priority This can be derived from
bits 10:8 in the Data Field (see below).
The Redirection Hint bit = 1 if bits 10:8 in the Delivery Mode field associated with corresponding
interrupt are encoded as 001 (Lowest Priority). Otherwise, the Redirection Hint bit = 0.
Destination Mode: This bit is used only the Redirection Hint bit = 1. If the Redirection Hint bit and
the Destination Mode bit are both set to 1, the logical destination mode is used and the redirection is
limited only to those processors that are part of the logical group as based on the logical ID.
Will always be 00.
5-58
82801BA ICH2 and 82801BAM ICH2-M Datasheet