82801BA Datasheet, PDF (108/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
vectors in the vector table. In this mode, the INTR output is not used and the microprocessor
internal Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll Command.
The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as an
interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads the priority level.
Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read
will contain a 1’ in bit 7 if there is an interrupt, and the binary code of the highest priority level in
bits 2:0.
Cascade Mode
The PIC in the ICH2 has one master 8259 and one slave 8259 cascaded onto the master through
IRQ2. This configuration can handle up to 15 separate priority levels. The master controls the
slaves through a 3-bit internal bus. In the ICH2, when the master drives 010b on this bus, the slave
controller takes responsibility for returning the interrupt vector. An EOI Command must be issued
twice: once for the master and once for the slave.
Edge-Triggered and Level-Triggered Mode
In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the
entire controller. In the ICH2, this bit is disabled and a new register for edge-triggered and level-
triggered mode selection, per interrupt input, is included. This is the Edge/Level control Registers
ELCR1 and ELCR2.
If an ELCR bit is 0’, an interrupt request will be recognized by a low to high transition on the
corresponding IRQ input. The IRQ input can remain high without generating another interrupt. If
an ELCR bit is 1’, an interrupt request will be recognized by a high level on the corresponding IRQ
input and there is no need for an edge detection. The interrupt request must be removed before the
EOI command is issued to prevent a second interrupt from occurring.
In both the edge-triggered and level-triggered modes, the IRQ inputs must remain active until after
the falling edge of the first internal INTA#. If the IRQ input goes inactive before this time, a default
IRQ7 vector will be returned.
End of Interrupt Operations
An EOI can occur in one of two fashions: by a command word write issued to the PIC before
returning from a service routine, the EOI command; or automatically when AEOI bit in ICW4 is
set to 1.
Normal End of Interrupt
In Normal EOI, software writes an EOI command before leaving the interrupt service routine to
mark the interrupt as completed. There are two forms of EOI commands: Specific and Non-
Specific. When a Non-Specific EOI command is issued, the PIC will clear the highest ISR bit of
those that are set to 1. Non-Specific EOI is the normal mode of operation of the PIC within the
ICH2, as the interrupt being serviced currently is the interrupt entered with the interrupt
acknowledge. When the PIC is operated in modes which preserve the fully nested structure,
software can determine which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked
will not be cleared by a Non-Specific EOI if the PIC is in the Special Mask Mode. An EOI
command must be issued for both the master and slave controller.
Automatic End of Interrupt Mode
In this mode, the PIC will automatically perform a Non-Specific EOI operation at the trailing edge
of the last interrupt acknowledge pulse. From a system standpoint, this mode should be used only
when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode
can only be used in the master controller and not the slave controller.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet