82801BA Datasheet, PDF (330/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.3.8 PM2_CNT—Power Management 2 Control (82801BAM ICH2-M)
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 20h
(ACPI PM2_BLK)
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI
Bit
Description
7:1 Reserved.
Arbiter Disable (ARB_DIS)— R/W.
0 = Enable system arbiter. The arbiter can grant the bus to bus masters (internal devices or external
PCI devices), other than the processor.
0 _{1 = Disable system arbiter (default). Processor has ownership of the system bus and memory. No}
bus masters (internal or external) are granted the bus. Note that after the arbiter is disabled, the
processor must not initiate any down-bound reads to PCI devices that may have up-bound
posted data, as this will result in system deadlock.
9.8.3.9
GPE0_STS—General Purpose Event 0 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 28h
(ACPI GPE0_BLK)
0000h
No
Resume
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI
Note:
This register is symmetrical to the General Purpose Event 0 Enable Register. If the corresponding
seen bit is set, then when the _STS bit get set, ICH2 generates a Wake Event. Once back in an S0
state (or if already in an S0 state when the event occurs), ICH2 also generates an SCI if the SCI_EN
bit is set, or an SMI# if the SCI_EN bit is not set. There will be no SCI/SMI# or wake event on
THRMOR_STS since there is no corresponding x_EN bit. None of these bits are reset by CF9h
write. All are reset by RSMRST#.
Bit
Description
15:12
11
10
Reserved.
PME Status (PME_STS)—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN bit is set, and
the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI or SMI#
(if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1–S4 state (or S5 state
due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a
wake event, and an SCI will be generated. If the system is in an S5 state due to power button
override or a power failure, then PME_STS will not cause a wake event or SCI.
ICH2 (82801BA):
Reserved
ICH2-M (82801BAM):
BATLOW_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the BATLOW# signal is asserted.
9-68
82801BA ICH2 and 82801BAM ICH2-M Datasheet