82801BA Datasheet, PDF (256/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.16
SECSTS—Secondary Status Register (HUB-PCI—D30:F0)
Offset Address: 1E–1Fh
Default Value: 0280h
Attribute:
Size:
R/W
16 bits
For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit will have no
effect.
Bit
Description
Detected Parity Error (DPE)—R/WC.
15 ^{1 = ICH2 detected a parity error on the PCI bus.}
0 = Software clears this bit by writing a 1 to the bit position.
Received System Error (SSE)—R/WC.
14 ^{1 = SERR# assertion is received on PCI.}
0 = Software clears this bit by writing a 1 to the bit position.
Received Master Abort (RMA)—R/WC.
13 ^{1 = Hub interface to PCI cycle is master-aborted on PCI.}
0 = Software clears this bit by writing a 1 to the bit position.
Received Target Abort (RTA)—R/WC.
1 = Hub interface to PCI cycle is target-aborted on PCI. For “completion required” cycles from the
hub interface, this event should also set the Signaled Target Abort in the Primary Status
12
Register in this device and the ICH2 must send the “target abort” status back to the hub
interface.
0 = Software clears this bit by writing a 1 to the bit position.
11 Signaled Target Abort (STA)—RO. The ICH2 does not generate target aborts.
DEVSEL# Timing Status—RO.
10:9
01h = Medium timing.
Data Parity Error Detected (DPD)—R/WC.
1 = The ICH2 sets this bit when all of the following three conditions are met:
- The Parity Error Response Enable bit in the Bridge Control Register (bit 0, offset 3Eh) is set
8
- USB, AC’97 or IDE is a Master
- PERR# asserts during a write cycle OR a parity error is detected internally during a read cycle
0 = Software clears this bit by writing a 1 to the bit position.
7
Fast Back to Back—RO. Hardwired to 1 to indicate that the PCI to hub interface target logic is
capable of receiving fast back-to-back cycles.
6 User Definable Features (UDF)—RO. Hardwired to 0.
5 66 MHz Capable—RO. Hardwired to 0.
4:0 Reserved.
8-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet