82801BA Datasheet, PDF (84/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.3.1.2 Start Field Definition
Table 5-4. Start Field Bit Definitions
Bits[3:0]
Encoding
0000
0010
0011
1111
Start of cycle for a generic target.
Grant for bus master 0.
Grant for bus master 1.
Stop/Abort: End of a cycle for a target.
Definition
NOTE: All other encodings are Reserved.
5.3.1.3 Cycle Type / Direction (CYCTYPE + DIR)
The ICH2 always drives bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0. Table 5-5 shows the valid bit encodings.
Table 5-5. Cycle Type Bit Definitions
Bits[3:2]
00
00
01
01
10
10
11
Bit[1]
0
1
0
1
0
1
x
Definition
I/O Read
I/O Write
Memory Read
Memory Write
DMA Read
DMA Write
Reserved. If a peripheral performing a bus master cycle generates this value, the
ICH2 will abort the cycle.
5.3.1.4 Size
Bits[3:2] are reserved. The ICH2 always drives them to 00. Peripherals running bus master cycles
are also supposed to drive 00 for bits 3:2; however, the ICH2 ignores those bits. Table 5-6 shows
the bit encodings for Bits[1:0].
Table 5-6. Transfer Size Bit Definition
Bits[1:0]
Size
00
8 bit transfer (1 byte)
01
16-bit transfer (2 bytes)
10
Reserved. The ICH2 never drives this combination. If a peripheral running a bus master cycle
drives this combination, the ICH2 may abort the transfer.
11
32 bit transfer (4 bytes)
5-22
82801BA ICH2 and 82801BAM ICH2-M Datasheet