82801BA Datasheet, PDF (189/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.16.6.2
Bit Stuff Error
A bit stuff error results from the detection of a sequence of more that 6 ones in a row within the
incoming data stream. This will cause the C_ERR field of the TD to be decremented. When the
C_ERR field decrements to zero, the Active bit in the TD is cleared to 0, the Stalled bit is set to 1,
the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the frame and a
hardware interrupt is signaled to the system.
Non-Transaction Based Interrupts
If an ICH2 process error or system error occur, the ICH2 halts and immediately issues a hardware
interrupt to the system.
Resume Received
This event indicates that the ICH2 received a RESUME signal from a device on the USB bus
during a global suspend. If this interrupt is enabled in the Interrupt Enable register, a hardware
interrupt will be signaled to the system allowing the USB to be brought out of the suspend state and
returned to normal operation.
ICH2 Process Error
The HC monitors certain critical fields during operation to ensure that it does not process corrupted
data structures. These include checking for a valid PID and verifying that the MaxLength field is
less than 1280. If it detects a condition that would indicate that it is processing corrupted data
structures, it immediately halts processing, sets the HC Process Error bit in the HC Status Register
and signals a hardware interrupt to the system.
This interrupt cannot be disabled through the Interrupt Enable Register.
Host System Error
The ICH2 sets this bit to 1 when a PCI Parity error, PCI Master Abort, or PCI Target Abort occurs.
When this error occurs, the ICH2 clears the Run/Stop bit in the Command Register to prevent
further execution of the scheduled TDs. This interrupt cannot be disabled through the Interrupt
Enable Register.
5.16.7 USB Power Management
The Host Controller can be put into a suspended state and its power can be removed. This requires
that certain bits of information are retained in the resume power plane of the ICH2 so that a device
on a port may wake the system. Such a device may be a fax-modem, that wakes up the machine to
receive a fax or takes a voice message. The settings of the following bits in I/O space is maintained
when the ICH2 enters the S3, S4 or S5 states.
Table 5-74. Bits maintained in low power states
Register
Command
Status
Port Status and Control
Offset
00h
02h
10h & 12h
Bit
Description
3 Enter Global Suspend Mode (EGSM)
2 Resume Detect
2 Port Enabled/Disabled
6 Resume Detect
8 Low Speed Device Attached
12 Suspend
When the ICH2 detects a resume event on any of its ports, it sets the corresponding USB_STS bit
in ACPI space. If USB is enabled as a wake/break event, the system wakes up and an SCI is
generated.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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