82801BA Datasheet, PDF (484/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

I/O Register Index
Table A-2. ICH2 Variable I/O Registers
Register Name
Offset
EDS Section and Location
LAN Control/Status Registers (CSR) may be mapped to either I/O space or memory space.
LAN CSR at CSR_IO_BASE + Offset or CSR_MEM_BASE + Offset. CSR_MEM_BASE set in
Section 7.1.11, “CSR_MEM_BASE CSR—Memory-Mapped Base Address Register (LAN Controller—
B1:D8:F0)” on page 7-5 CSR_IO_BASE set in Section 7.1.12, “CSR_IO_BASE—CSR I/O-Mapped Base
Address Register (LAN Controller—B1:D8:F0)” on page 7-5
SCB Status Word
SCB Command Word
SCB General Pointer
PORT
EEPROM Control Register
MDI Control Register
Receive DMA Byte Count
Early Receive Interrupt
Flow Control Register
PMDR
General Control
General Status
01h–00h
03h–02h
07h–04h
OBh–08h
0Fh–0Eh
13h–10h
17h–14h
18h
1Ah–19h
1Bh
1Ch
1Dh
Section 7.2.1, “System Control Block Status Word
Register” on page 7-11
Section 7.2.2, “System Control Block Command Word
Register” on page 7-12
Section 7.2.3, “System Control Block General Pointer
Register” on page 7-14
Section 7.2.4, “PORT Register” on page 7-14
Section 7.2.5, “EEPROM Control Register” on
page 7-15
Section 7.2.6, “Management Data Interface (MDI)
Control Register” on page 7-16
Section 7.2.7, “Receive DMA Byte Count Register” on
page 7-16
Section 7.2.8, “Early Receive Interrupt Register” on
page 7-17
Section 7.2.9, “Flow Control Register” on page 7-18
Section 7.2.10, “Power Management Driver (PMDR)
Register” on page 7-19
Section 7.2.11, “General Control Register” on
page 7-19
Section 7.2.12, “General Status Register” on
page 7-20
Power Management I/O Registers at PMBASE+Offset
PMBASE set in Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 9-6
PM1 Status
PM1 Enable
PM1 Control
PM1 Timer
Processor Control
Level 2 Register
General Purpose Event 0 Status
General Purpose Event 0 Enables
General Purpose Event 1 Status
General Purpose Event 1 Enables
00–01h
02–03h
04–07h
08–0Bh
10h–13h
14h
28–29h
2A–2Bh
2C–2D
2E–2F
Section 9.8.3.1, “PM1_STS—Power Management 1
Status Register” on page 9-62
Section 9.8.3.2, “PM1_EN—Power Management 1
Enable Register” on page 9-64
Section 9.8.3.3, “PM1_CNT—Power Management 1
Control Register” on page 9-65
Section 9.8.3.4, “PM1_TMR—Power Management 1
Timer Register” on page 9-66
Section 9.8.3.5, “PROC_CNT—Processor Control
Register” on page 9-66
Section 9.8.3.6, “LV2—Level 2 Register” on
page 9-67
Section 9.8.3.9, “GPE0_STS—General Purpose
Event 0 Status Register” on page 9-68
Section 9.8.3.10, “GPE0_EN—General Purpose
Event 0 Enables Register” on page 9-70
Section 9.8.3.11, “GPE1_STS—General Purpose
Event 1 Status Register” on page 9-71
Section 9.8.3.12, “GPE1_EN—General Purpose
Event 1 Enable Register” on page 9-72
A-6
82801BA ICH2 and 82801BAM ICH2-M Datasheet