82801BA Datasheet, PDF (320/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.1.5
TRP_FWD_EN—IO Monitor Trap Forwarding Enable Register
(PM—D31:F0)
Offset Address:
Default Value:
Lockable:
Power Well:
C0h
00h
No
Core
Attribute:
Size:
Usage:
R/W (Special)
8 bits
Legacy Only
The ICH2 uses this register to enable the monitors to forward cycles to LPC, independent of the
POS_DEC_EN bit and the bits that enable the monitor to generate an SMI#. The only criteria is
that the address passes the decoding logic as determined by the MON[n]_TRP_RNG and
MON_TRP_MSK register settings.
Bit
Description
Monitor 7 Forward Enable (MON7_FWD_EN)—R/W.
7
0 = Disable. Cycles trapped by I/O Monitor 7 will not be forwarded to LPC.
1 = Enable. Cycles trapped by I/O Monitor 7 will be forwarded to LPC.
Monitor 6 Forward Enable (MON6_FWD_EN)—R/W.
6
0 = Disable. Cycles trapped by I/O Monitor 6 will not be forwarded to LPC.
1 = Enable. Cycles trapped by I/O Monitor 6 will be forwarded to LPC.
Monitor 5 Forward Enable (MON5_FWD_EN)—R/W.
5
0 = Disable. Cycles trapped by I/O Monitor 5 will not be forwarded to LPC.
1 = Enable. Cycles trapped by I/O Monitor 5 will be forwarded to LPC.
Monitor 4 Forward Enable (MON4_FWD_EN)—R/W.
4
0 = Disable. Cycles trapped by I/O Monitor 4 will not be forwarded to LPC.
1 = Enable. Cycles trapped by I/O Monitor 4 will be forwarded to LPC.
3:0 Reserved.
9-58
82801BA ICH2 and 82801BAM ICH2-M Datasheet