82801BA Datasheet, PDF (418/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

AC’97 Modem Controller Registers (D31:F6)
Table 14-3. Modem Registers
Offset
00h
04h
05h
06h
08h
0Ah
0Bh
10h
14h
15h
16h
18h
1Ah
1Bh
3Ch
40h
44h
Mnemonic
MI_BDBAR
MI_CIV
MI_LVI
MI_SR
MI_PICB
MI_PIV
MI_CR
MO_BDBAR
MO_CIV
MO_LVI
MO_SR
MI_PICB
MO_PIV
MO_CR
GLOB_CNT
GLOB_STA
ACC_SEMA
Name
Modem In Buffer Descriptor List Base Address
Register
Modem In Current Index Value Register
Modem In Last Valid Index Register
Modem In Status Register
Modem In Position In Current Buffer Register
Modem In Prefetch Index Value Register
Modem In Control Register
Modem Out Buffer Descriptor List Base Address
Register
Modem Out Current Index Value Register
Modem Out Last Valid Register
Modem Out Status Register
Modem In Position In Current Buffer Register
Modem Out Prefetched Index Register
Modem Out Control Register
Global Control
Global Status
Codec Write Semaphore Register
NOTE:
1. MI = Modem in channel; MO = Modem out channel
Default
Access
00000000h
00h
00h
0001h
00h
00h
00h
00000000h
00h
00h
0001h
00h
00h
00h
00000000h
00000000h
00h
R/W
R
R/W
R/W
R
RO
R/W
R/W
RO
R/W
R/W
RO
RO
R/W
R/W
RO
R/W
14.2.1
x_BDBAR—Buffer Descriptor List Base Address Register
I/O Address:
Default Value:
Lockable:
MBAR + 00h (MIBDBAR),
MBAR + 10h (MOBDBAR)
00000000h
No
Attribute:
Size:
Power Well:
R/W (DWord access only)
32bits
Core
This register can be accessed only as a DWord (32 bits).
Bit
Description
31:3
Buffer Descriptor List Base Address[31:3]—R/W. These bits represent address bits 31:3. The
entries should be aligned on 8 byte boundaries.
2:0 Hardwired to 0.
14-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet