82801BA Datasheet, PDF (164/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Line Buffer
A single line buffer exists for the ICH2 Bus master IDE interface. This buffer is not shared with
any other function. The buffer is maintained in either the read state or the write state. Memory
writes are typically 4-DWord bursts and invalid DWords have C/BE[3:0]#=0Fh. The line buffer
allows burst data transfers to proceed at peak transfer rates.
The Bus Master IDE Active bit in Bus Master IDE Status register is reset automatically when the
controller has transferred all data associated with a Descriptor Table (as determined by EOT bit in
last PRD). The IDE Interrupt Status bit is set when the IDE device generates an interrupt. These
events may occur prior to line buffer emptying for memory writes. If either of these conditions
exist, all PCI Master non-memory read accesses to ICH2 are retried until all data in the line buffers
has been transferred to memory.
Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The
DMA Timing Enable Only bits in IDE Timing register can be used to program fast timing mode for
DMA transactions only. This is useful for IDE devices whose DMA transfer timings are faster that
its PIO transfer timings. The IDE device DMA request signal is sampled on the same PCI clock
that DIOR# or DIOW# is deasserted. If inactive, the DMA Acknowledge signal is deasserted on
the next PCI clock and no more transfers take place until DMA request is asserted again.
Interrupts
The ICH2 is connected to IRQ14 for the primary interrupt and IRQ15 for the secondary interrupt.
This connection is done from the ISA pin, before any mask registers. This implies the following:
• Bus Master IDE is operating under an interrupt based driver. Therefore, it does not operate
under environments where the IDE device drives an interrupt but the interrupt is masked in the
system.
• Bus Master IDE devices are connected directly off of ICH2. IDE interrupts cannot be
communicated through PCI devices or the serial stream.
Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following steps are
required:
1. Software prepares a PRD Table in system memory. The PRD Table must be DWord aligned
and must not cross a 64 KB boundary.
2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer
Register. The direction of the data transfer is specified by setting the Read/Write Control bit.
The interrupt bit and Error bit in the Status register are cleared.
3. Software issues the appropriate DMA transfer command to the disk device.
4. The bus master function is engaged by software writing a '1' to the Start bit in the Command
Register. The first entry in the PRD table is fetched and loaded into two registers which are not
visible by software, the Current Base and Current Count registers. These registers hold the
current value of the address and byte count loaded from the PRD table. The value in these
registers is only valid when there is an active command to an IDE device.
5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet