82801BA Datasheet, PDF (479/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

I/O Register Index
I/O Register Index
A
Table A-1. ICH2 Fixed I/O Registers
Register Name
Channel 0 DMA Base & Current
Address Register
Channel 0 DMA Base & Current
Count Register
Channel 1 DMA Base & Current
Address Register
Channel 1 DMA Base & Current
Count Register
Channel 2 DMA Base & Current
Address Register
Channel 2 DMA Base & Current
Count Register
Channel 3 DMA Base & Current
Address Register
Channel 3 DMA Base & Current
Count Register
Channel 0–3 DMA Command
Register
Channel 0–3 DMA Status Register
Channel 0–3 DMA Write Single
Mask Register
Channel 0–3 DMA Channel Mode
Register
Channel 0–3 DMA Clear Byte
Pointer Register
Channel 0–3 DMA Master Clear
Register
Channel 0–3 DMA Clear Mask
Register
Channel 0–3 DMA Write All Mask
Register
Aliased at 00h–0Fh
Master PIC ICW1 Init. Cmd Word 1
Register
Master PIC OCW2 Op Ctrl Word 2
Register
Master PIC OCW3 Op Ctrl Word 3
Register
Port
00h
01h
02h
03h
04h
05h
06h
07h
08h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h–1Fh
20h
EDS Section and Location
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers” on page 9-24
Section 9.2.2, “DMABASE_CC—DMA Base and Current
Count Registers” on page 9-25
Section 9.2.4, “DMACMD—DMA Command Register”
on page 9-26
Section 9.2.5, “DMASTS—DMA Status Register” on
page 9-26
Section 9.2.6, “DMA_WRSMSK—DMA Write Single
Mask Register” on page 9-27
Section 9.2.7, “DMACH_MODE—DMA Channel Mode
Register” on page 9-27
Section 9.2.8, “DMA Clear Byte Pointer Register” on
page 9-28
Section 9.2.9, “DMA Master Clear Register” on
page 9-28
Section 9.2.10, “DMA_CLMSK—DMA Clear Mask
Register” on page 9-28
Section 9.2.11, “DMA_WRMSK—DMA Write All Mask
Register” on page 9-29
Section 9.4.2, “ICW1—Initialization Command Word 1
Register” on page 9-34
Section 9.4.8, “OCW2—Operational Control Word 2
Register” on page 9-37
Section 9.4.9, “OCW3—Operational Control Word 3
Register” on page 9-38
82801BA ICH2 and 82801BAM ICH2-M Datasheet
A-1