82801BA Datasheet, PDF (266/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.1.4
9.1.5
PCISTS—PCI Device Status (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
06–07h
0280h
No
Attribute:
Size:16-bit
Power Well:
R/WC
Core
Bit
Description
15
14
13
12
11
10:9
8
7
6
5
4:0
Detected Parity Error (DPE)—R/W.
1 = PERR# signal goes active. Set even if the PER bit is 0.
0 = This bit is cleared by software writing a 1 to the bit position.
Signaled System Error (SSE)—R/W.
1 = Set by the ICH2 if the SERR_EN bit is set and the ICH2 generates an SERR# on function 0. The
ERR_STS register can be read to determine the cause of the SERR#. The SERR# can be routed
to cause SMI#, NMI, or interrupt.
0 = This bit is cleared by software writing a 1 to the bit position.
Master Abort Status (RMA)—R/W.
1 = ICH2 generated a master abort on PCI due to LPC I/F master or DMA cycles.
0 = This bit is cleared by software writing a 1 to the bit position.
Received Target Abort (RTA)—R/W.
1 = ICH2 received a target abort during LPC I/F master or DMA cycles to PCI.
0 = This bit is cleared by software writing a 1 to the bit position.
Signaled Target Abort (STA)—R/W.
1 = ICH2 generated a target abort condition on PCI cycles claimed by the ICH2 for ICH2 internal
registers or for going to LPC I/F.
0 = This bit is cleared by software writing a 1 to the bit position.
DEVSEL# Timing Status (DEV_STS)—RO.
01 = Medium Timing.
Data Parity Error Detected (DPED)—R/WC.
1 = Set when all three of the following conditions are true:
- The ICH2 is the initiator of the cycle,
- The ICH2 asserted PERR# (for reads) or observed PERR# (for writes), and
- The PER bit is set.
0 = This bit is cleared by software writing a 1 to the bit position.
Fast Back to Back (FB2B)—RO. Always 1. Indicates ICH2 as a target can accept fast back-to-back
transactions.
User Definable Features (UDF). Hardwired to 0
66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0
Reserved.
REVID—Revision ID Register (LPC I/F—D31:F0)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
Revision Identification Number. 8-bit value that indicates the revision number for the LPC bridge.
7:0 For the A-0 stepping, this value is 00h. Refer to the Specification Update for the value of the Revision
ID Register
9-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet