82801BA Datasheet, PDF (374/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

USB Controller Registers
11.2 USB I/O Registers
Some of the read/write register bits that deal with changing the state of the USB hub ports function
such that on read back they reflect the current state of the port, and not necessarily the state of the
last write to the register. This allows the software to poll the state of the port and wait until it is in
the proper state before proceeding. A Host Controller Reset, Global Reset, or Port Reset will
immediately terminate a transfer on the affected ports and disable the port. This affects the
USBCMD register, bit [4] and the PORTSC registers, bits [12,6,2]. See individual bit descriptions
for more detail.
Table 11-2. USB I/O Registers
Offset
Mnemonic
Register
00–01h
02–03h
04–05h
06–07h
08–0Bh
0Ch
0D–0Fh
10–11h
12–13h
14–17h
18h
USBCMD
USBSTS
USBINTR
FRNUM
FRBASEADD
SOFMOD
—
PORTSC0
PORTSC1
—
LOOPDATA
USB Command Register
USB Status Register
USB Interrupt Enable
USB Frame Number
USB Frame List Base Address
USB Start of Frame Modify
Reserved
Port 0 Status/Control
Port 1 Status/Control
Reserved
Loop Back Test Data
Default
0000h
0020h
0000h
0000h
Undefined
40h
0
0080h
0080h
0
00h
Type
R/W*
R/WC
R/W
R/W (see Note 1)
R/W
R/W
RO
R/WC (see Note 1)
R/WC (see Note 1)
RO
RO
NOTES:
1. These registers are Word writable only. Byte writes to these registers have unpredictable effects.
11.2.1
USBCMD—USB Command Register
I/O Offset:
Default Value:
Base + (00–01h)
0000h
Attribute:
Size:
R/W
16 bits
The Command Register indicates the command to be executed by the serial bus host controller.
Writing to the register causes a command to be executed. The table following the bit description
provides additional information on the operation of the Run/Stop and Debug bits.
Bit
Description
15:7 Reserved.
Loop Back Test Mode—R/W.
1 = ICH2 is in loop back test mode. When both ports are connected together, a write to one port will
8
be seen on the other port and the data will be stored in I/O offset 18h.
0 = Disable loop back test mode.
Max Packet (MAXP)—R/W. This bit selects the maximum packet size that can be used for full
speed bandwidth reclamation at the end of a frame. This value is used by the Host Controller to
determine whether it should initiate another transaction based on the time remaining in the SOF
counter. Use of reclamation packets larger than the programmed size will cause a Babble error if
7 ^{executed during the critical window at frame end. The Babble error results in the offending endpoint}
being stalled. Software is responsible for ensuring that any packet which could be executed under
bandwidth reclamation be within this size limit.
1 = 64 bytes
0 = 32 bytes
11-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet