82801BA Datasheet, PDF (134/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.12.1 ICH2 and System Power States
Table 5-36 shows the power states defined for ICH2-based platforms. The state names generally
match the corresponding ACPI states.
Table 5-36. General Power States for Systems using ICH2
State/
Substates
Legacy Name / Description
G0/S0/C0
Full On: Processor operating. Individual devices may be shut down to save power. The
different processor operating levels are defined by Cx states, as shown in Table 5-37. Within
the C0 state, the ICH2 can throttle the STPCLK# signal to reduce power consumption. The
throttling can be initiated by software or by the THRM# input signal.
G0/S0/C1
Auto-Halt: The processor has executed an AutoHalt instruction and is not executing code.
The processor snoops the bus and maintains cache coherency.
G0/S0/C2
Stop-Grant (ICH2) / Quickstart (ICH2-M): The STPCLK# signal goes active to the
processor. The processor performs a Stop-Grant cycle, halts its instruction stream, and
remains in that state until the STPCLK# signal goes inactive. In the Stop-Grant (ICH2) /
Quickstart (ICH2-M) state, the processor snoops the bus and maintains cache coherency.
G0/S0/C3
(ICH2-M only)
Stop-Clock: The STPCLK# signal goes active to the processor. The processor performs a
Stop-Grant cycle, halts its instruction stream. ICH2-M then asserts STP_CPU#, which forces
the clock generator to stop the processor clock. This is also used for Intel^® SpeedStep^TM
technology support. Accesses to memory (by AGP, PCI, or internal units) is not permitted
while in a C3 state. It is assumed that the ARB_DIS bit is set prior to entering C3 state.
G1/S1
(ICH2 only)
Stop-Grant: Similar to G0/S0/C2 state. The ICH2 also has the option to assert the CPUSLP#
signal to further reduce processor power consumption.
Note: The behavior for this state is slightly different when supporting iA64 processors.
G1/S1
(ICH2-M only)
Powered-On-Suspend (POS): In this state, all clocks (except the 32.768 kHz clock) are
stopped. The system context is maintained in system DRAM. Power is maintained to PCI, the
processor, memory controller, memory, and all other criticial subsystems. Note that this state
does not preclude power being removed from non-essential devices (e.g., disk drives).
G1/S3
Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is
shut off to non-critical circuits. Memory is retained and refreshes continue. All clocks stop
except RTC clock.
G1/S4
Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is
then shut off to the system except for the logic required to resume. Externally appears same
as S5, but may have different wake events.
G2/S5
Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic
required to restart. A full boot is required when waking.
Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the
RTC. No “Wake” events are possible, because the system does not have any power. This
G3
state occurs if the user removes the batteries, turns off a mechanical switch, or if the system
power supply is at a level that is insufficient to power the “waking” logic. When system power
returns, transition depends on the state just prior to the entry to G3 and the AFTERG3 bit in
the GEN_PMCON3 register (D31:F0, offset A4). Refer to Table 5-45 for more details.
Table 5-37 shows the transitions rules among the various states. Note that transitions among the
various states may appear to temporarily transition through intermediate states. For example, in
going from S0 to S1, it may appear to pass through the G0/S0/C2 states. These intermediate
transitions and states are not listed in the table.
5-72
82801BA ICH2 and 82801BAM ICH2-M Datasheet