82801BA Datasheet, PDF (144/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Upon exit from the ICH2-controlled Sleep states, the WAK_STS bit will be set. The possible
causes of Wake Events (and their restrictions) are shown in Table 5-42.
Notes:
• If in the S5 state due to a powerbutton override, the only wake event is power button.
• For the ICH2-M, if the BATLOW# signal is asserted, the ICH2-M will not attempt to wake
from an S1 (Mobile) – S5 state, even if the power button is pressed. This prevents the system
from waking when the battery power is insufficient to wake the system. Wake events that
occur while BATLOW# is asserted are latched by the ICH2-M, and the system wakes after
BATLOW# is deasserted.
Table 5-42. Causes of Wake Events
Cause
RTC Alarm
Power Button
GPI[0:n]
USB
LAN
RI#
AC97
PME#
GST Timeout
SMBALERT#
SMBus Slave Message
States Can
Wake From
S1–S5
(Note 1)
S1–S5
S1–S5
(Note 1)
S1–S4
S1–S5
S1–S5
(Note 1)
S1–S5
S1–S5
(Note 1)
S1M
S1–S4
S1–S5
How Enabled
Set RTC_EN bit in PM1_EN Register
Always enabled as Wake event
GPE1_EN register
Set USB1_EN and USB2_EN bits in GPE0_EN Register
Will use PME#. Wake enable set with LAN logic.
Set RI_EN bit in GPE0_EN Register
Set AC97_EN bit in GPE0_EN Register
Set PME_EN bit in GPE0_EN Register.
Setting the GST Timeout range to a value other than 00h.
SMB_WAK_EN in the GPE0 Register
Always enabled as a Wake Event
NOTES:
1. This will be a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP
bits via software.
It is important to understand that the various GPIs have different levels of functionality when used
as wake events. The GPIs that reside in the core power well can only generate wake events from an
S1 state. Also, only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits
reside in ACPI I/O space. Table 5-43 summarizes the use of GPIs as wake events.
Table 5-43. GPI Wake Events
GPI
GPI[7:0], GPI[23:16]
GPI[15:8]
Power Well
Core
Resume
Wake From
S1
S1–S5
Notes
ACPI Compliant
The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply
design. Approximations are shown in Table 5-44. The time indicates from when the Wake event
occurs (signal transition) to when the processor is allowed to start its first cycle (CPURST# goes
inactive). There will be very large additional delays for the processor to execute sufficient amounts
of BIOS to invoke the OS (such as coming out of S1–S3) or spinning up the hard drive
(e.g., coming out of S4 or S5).
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82801BA ICH2 and 82801BAM ICH2-M Datasheet