82801BA Datasheet, PDF (143/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.12.7 Sleep States
The ICH2 directly supports different sleep states (S1–S5), which are entered by setting the
SLP_EN bit, or due to a Power Button press. The entry to the Sleep states are based on several
assumptions:
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because the
processor can only perform one register access at a time. A request to Sleep always has higher
priority than throttling.
• Prior to setting the SLP_EN bit, the software turns off processor-controlled throttling. Note
that thermal throttling cannot be disabled, but setting the SLP_EN bit will disable thermal
throttling (since S1–S5 sleep state has higher priority).
• The G3 state cannot be entered via any software mechanism. The G3 state indicates a
complete loss of power.
5.12.7.1 Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• Masking interrupts, turning off all bus master enable bits, setting the desired type in the
SLP_TYP field, and then setting the SLP_EN bit. The hardware will then attempt to gracefully
put the system into the corresponding Sleep state by first going to a C2 (C2 or C3 for the
ICH2-M) state. See Section 5.12.5 for details on going to the C2 (C2 or C3 for the ICH2-M)
state.
• Pressing the PWRBTN# signal for more than 4 seconds to cause a Power Button Override
event. In this case the transition to the S5 state will be less graceful, since there will be no
dependencies on observing Stop-Grant cycles from the processor or on clocks other than the
RTC clock.
Table 5-41. Sleep Types
Sleep Type
S1
(ICH2 only)
S1
(ICH2-M only)
S3
S4
S5
Comment
ICH2 asserts the CPUSLP# signal. This lowers the processor’s power consumption. No
snooping is possible in this state.
ICH2-M asserts the SLP_S1# signal. This can be connected to the system clock generator
to either put it into a low-power mode or to remove its power altogether. No snooping is
possible in this state.
ICH2 asserts SLP_S3# (ICH2-M asserts SLP_S1# and SLP_S3#). The SLP_S3# signal
controls the power to non-critical circuits. Power is only be retained to devices needed to
wake from this sleeping state, as well as to the memory.
ICH2 asserts SLP_S3# and SLP_S5# (ICH2-M asserts SLP_S1#, SLP_S3# and
SLP_S5#). The SLP_S5# signal shuts off the power to the memory subsystem. Only
devices needed to wake from this state should be powered.
Same as S4. ICH2 asserts SLP_S3# and SLP_S5# (ICH2-M asserts SLP_S1#, SLP_S3#
and SLP_S5#). The SLP_S5# signal shuts off the power to the memory subsystem. Only
devices needed to wake from this state should be powered.
5.12.7.2
Exiting Sleep States
Sleep states (S10–S5) are exited based on Wake events. The Wake events will force the system to a
full on state (S0), although some non-critical subsystems might still be shut off and have to be
brought back manually. For example, the hard disk may be shut off during a sleep state, and have to
be enabled via a GPIO pin before it can be used.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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