82801BA Datasheet, PDF (10/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

5.12.10 Event Input Signals and Their Usage ............................................5-87
5.12.10.1 PWRBTN# — Power Button...........................................5-87
5.12.10.2 RI# — Ring Indicate .......................................................5-88
5.12.10.3 PME# — PCI Power Management Event.......................5-88
5.12.10.4 AGPBUSY# (82801BAM ICH2-M) .................................5-88
5.12.11 Alt Access Mode ............................................................................5-89
5.12.11.1 Write Only Registers with Read Paths in
Alternate Access Mode ..................................................5-89
5.12.11.2 PIC Reserved Bits ..........................................................5-91
5.12.11.3 Read Only Registers with Write Paths in
Alternate Access Mode ..................................................5-91
5.12.12 System Power Supplies, Planes, and Signals ...............................5-91
5.12.13 Clock Generators ...........................................................................5-93
5.12.13.1 Clock Control Signals from ICH2-M to Clock
Synthesizer (82801BAM ICH2-M only) ..........................5-93
5.12.14 Legacy Power Management Theory of Operation .........................5-94
5.12.14.1 Desktop APM Power Management
(82801BA ICH2 only) .....................................................5-94
5.12.14.2 Mobile APM Power Management
(82801BAM ICH2-M only) ..............................................5-94
5.13 System Management (D31:F0)...................................................................5-95
5.13.1 Theory of Operation.......................................................................5-95
5.13.2 Alert on LAN* .................................................................................5-96
5.14 General Purpose I/O...................................................................................5-98
5.15 IDE Controller (D31:F1) ..............................................................................5-99
5.15.1 PIO Transfers ................................................................................5-99
5.15.2 Bus Master Function ....................................................................5-101
5.15.3 Ultra ATA/33 Protocol ..................................................................5-105
5.15.4 Ultra ATA/66 Protocol ..................................................................5-107
5.15.5 Ultra ATA/100 Protocol ................................................................5-107
5.15.6 Ultra ATA/33/66/100 Timing ........................................................5-107
5.15.7 Mobile IDE Swap Bay (82801BAM ICH2-M only) ........................5-107
5.16 USB Controller (Device 31:Functions 2 and 4) .........................................5-108
5.16.1 Data Structures in Main memory .................................................5-108
5.16.1.1 Frame List Pointer ........................................................5-108
5.16.1.2 Transfer Descriptor (TD) ..............................................5-109
5.16.1.3 Queue Head (QH) ........................................................5-113
5.16.2 Data Transfers To/From Main Memory........................................5-114
5.16.2.1 Executing the Schedule................................................5-114
5.16.2.2 Processing Transfer Descriptors ..................................5-114
5.16.2.3 Command Register, Status Register, and TD
Status Bit Interaction ....................................................5-115
5.16.2.4 Transfer Queuing .........................................................5-116
5.16.3 Data Encoding and Bit Stuffing....................................................5-119
5.16.4 Bus Protocol ................................................................................5-120
5.16.4.1 Bit Ordering ..................................................................5-120
5.16.4.2 SYNC Field...................................................................5-120
5.16.4.3 Packet Field Formats ...................................................5-120
5.16.4.4 Address Fields..............................................................5-121
5.16.4.5 Frame Number Field ....................................................5-122
5.16.4.6 Data Field .....................................................................5-122
5.16.4.7 Cyclic Redundancy Check (CRC) ................................5-122
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82801BA ICH2 and 82801BAM ICH2-M Datasheet