82801BA Datasheet, PDF (86/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
When recognizing the SYNC field indicating an error, the ICH2 treats this the same as IOCHK#
going active on the ISA bus.
5.3.1.8 LFRAME# Usage
Start of Cycle
For Memory, I/O, and DMA cycles, the ICH2 asserts LFRAME# for 1 clock at the beginning of the
cycle (Figure 5-7) During that clock, the ICH2 drives LAD[3:0] with the proper START field.
Figure 5-7. Typical Timing for LFRAME#
LCLK
LFRAME#
LAD[3:0]#
Start
ADDR
1 CYCTYPE 1 - 8
Clock Dir & Size Clocks
TAR Sync
2
1-n
Clocks Clocks
Data
2
Clocks
TAR
2
Clocks
Start
1
Clock
Abort Mechanism
When performing an Abort, the ICH2 drives LFRAME# active for 4 consecutive clocks. On the 4^th
clock, the ICH2 drives LAD[3:0] to ‘1111b’.
Figure 5-8. Abort Mechanism
LCLK
LFRAME#
LAD[3:0]#
Start
ADDR
CYCTYPE
Dir & Size
TAR _Sync
Peripheral must
stop driving
Too many
Syncs causes
timeout
Chipset will
drive high
The ICH2 performs an abort for the following cases (possible failure cases):
• ICH2 starts a Memory, I/O, or DMA cycle and no device drives a valid SYNC after 4
consecutive clocks.
• ICH2 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.
• A peripheral drives an illegal address when performing bus master cycles.
• A peripheral drives an invalid value.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet