82801BA Datasheet, PDF (200/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.17.4 SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enabled and the signal is asserted, the ICH2
can generate an interrupt, an SMI#, or a wake event from S1-S4. To resume using SMBALERT#,
the SMB_SMI_EN bit must be enabled to generate an SMI (see Section 12.1.14, “HOSTC—Host
Configuration Register (SMBUS—D31:F3)” on page 12-5).
Note: As long as SMBALERT# is enabled and asserted, the ICH2 will continue to assert PIRQ[B]# or
SMI# (depending on the state of the SMB_SMI_EN bit). To avoid continuous SMIs or interrupts,
the interrupt or SMI handler should:
1. Disable SMBALERT# by setting GPIO_USE_SEL[11] (GPIOBase + 00h, bit 11)
2. Use the SMBus Host Controller to service the peripheral that is asserting SMBALERT#
(causing the device to deassert the signal)
3. Re-enable SMBALERT# by clearing GPIO_USE_SEL[11].
5.17.5
SMBus Slave Interface
The ICH2’s SMBus Slave interface is accessed via the SMLINK[1:0] signals. The slave interface
allows the ICH2 to decode cycles and allows an external microcontroller to perform specific
actions. Key features and capabilities include:
• Supports decode of two messages type: Write and Read
• Receive Slave Address register: This is the address that the ICH2 decodes. A default value is
provided so that the slave interface can be used without the processor having to program this
register.
• Receive Slave Data register in the SMBus I/O space that includes the data written by the
external microcontroller
• Registers that the external microcontroller can read to get the state of the ICH2. See Table 5-87
• Status bit to indicate that the SMBus logic caused an SMI# due to the reception of a message
that matched the slave address. See Section 9.8.3.14.
5-138
82801BA ICH2 and 82801BAM ICH2-M Datasheet