82801BA Datasheet, PDF (336/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.3.14
SMI_STS—SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 34h
0000h
No
Core
Attribute:
Size:
Usage:
R/W
32-bit
ACPI or Legacy
Note: If the corresponding _EN bit is set when the _STS bit is set, the ICH2 will cause an SMI# (except
bits 8:10 and 12, which do not need enable bits since they are logic ORs of other registers that have
enable bits).
Bit
Description
31:17 Reserved
SMBus SMI Status (SMBUS_SMI_STS)—R/WC.
1 = Indicates that the SMI# was caused by either the SMBus Slave receiving a message, or the
16
SMBALERT# signal going active. This bit will be set on SMBALERT# assertion only if the
SMBus Host Controller is programmed to generate SMIs (not interrupts).
0 = This bit is cleared by writing a 1 to its bit position.
SERR IRQ SMI Status (SERIRQ_SMI_STS)—RO.
15 ^{1 = Indicates that the SMI# was caused by the SERIRQ decoder.}
0 = SMI# was not caused by SERIRQ decoder. This is not a sticky bit.
Periodic Status (PERIODIC_STS)—R/WC.
1 = This bit will be set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit is
14
also set, the ICH2 will generate an SMI#.
0 = This bit is cleared by writing a 1 to its bit position.
TCO Status (TCO_STS)—RO.
13 _{0 = SMI# not caused by TCO logic.}
1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake event.
Device Monitor Status (DEVMON_STS)—RO.
1 = Set under any of the following conditions:
- Any of the DEV[7:4]_TRAP_STS bits are set and the corresponding DEV[7:4]_TRAP_EN bits
12
are also set.
- Any of the DEVTRAP_STS bits are set and the corresponding DEVTRAP_EN bits are also set.
0 = SMI# not caused by Device Monitor.
Microcontroller SMI# Status (MCSMI_STS)—R/WC.
0 = Indicates that there has been no access to the power management microcontroller range (62h or
11
66h). This bit is cleared by software writing a 1 to the bit position.
1 = Set if there has been an access to the power management microcontroller range (62h or 66h). If
this bit is set, and the MCSMI_EN bit is also set, the ICH2 will generate an SMI#.
GPE1 Status (GPE1_STS)—RO. This bit is a logical OR of the bits in the GPE1_STS register that
are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and have the
corresponding bit set in the GPE1_EN register. Bits that are not routed to cause an SMI# will have no
10 _{effect on the GPE1_STS bit.}
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
GPE0 Status (GPE0_STS)—RO. This bit is a logical OR of the bits in the GPE0_STS register that
also have the corresponding bit set in the GPE0_EN register.
9
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
PM1 Status Register (PM1_STS_REG)—RO. This is an OR of the bits in the ACPI PM1 Status
Register (offset PMBASE+00h) that can cause an SMI#.
8
0 = SMI# was not generated by a PM1_STS event.
1 = SMI# was generated by a PM1_STS event.
7 Reserved.
9-74
82801BA ICH2 and 82801BAM ICH2-M Datasheet