82801BA Datasheet, PDF (69/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Feature Summary
• Compliance with Advanced Configuration and Power Interface and PCI Power Management
standards
• Support for wake-up on interesting packets and link status change
• Support for remote power-up using Wake on LAN* (WOL) technology
• Deep power-down mode support
• Support of Wired for Management (WfM) Rev 2.0
• Backward compatible software with 82557, 82558 and 82559
• TCP/UDP checksum offload capabilities
• Support for Intel’s Adaptive Technology
5.2.1 LAN Controller Architectural Overview
Figure 5-4 is a high level block diagram of the ICH2 integrated LAN Controller. It is divided into
four main subsystems: a Parallel subsystem, a FIFO subsystem and the Carrier-Sense Multiple
Access with Collision Detect (CSMA/CD) unit.
Figure 5-4. Integrated LAN Controller Block Diagram
EEPROM
Interface
PCI
Interface
PCI Target and
EEPROM Interface
3 Kbyte
Tx FIFO
Four Channel
Addressing Unit -
DMA
PCI Bus
Interface Unit
(BIU)
Data Interface Unit
(DIU)
Micro-
machine
Dual
Ported
FIFO
FIFO Control
3 Kbyte
Rx FIFO
CSMA/CD
Unit
LAN
Connect
Interface
Parallel Subsystem Overview
The parallel subsystem is divided into several functional blocks: a PCI bus master interface, a
micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/
EEPROM/ interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data
(e.g., transmit, receive, and configuration data) and command and status parameters between these
two blocks.
The PCI bus master interface provides a complete interface to the PCI bus and is compliant with
the PCI Bus Specification, Revision 2.2. The LAN Controller provides 32 bits of addressing and
data, as well as the complete control interface to operate on the PCI bus. As a PCI target, it follows
the PCI configuration format which allows all accesses to the LAN Controller to be automatically
mapped into free memory and I/O space upon initialization of a PCI system. For processing of
transmit and receive frames, the integrated LAN Controller operates as a master on the PCI bus,
initiating zero wait state transfers for accessing these data parameters.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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