82801BA Datasheet, PDF (25/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

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Data Packet Format ..................................................................................5-124
Bits maintained in low power states..........................................................5-127
USB Legacy Keyboard State Transitions..................................................5-129
Quick Protocol...........................................................................................5-131
Send / Receive Byte Protocol ...................................................................5-131
Write Byte/Word Protocol..........................................................................5-132
Read Byte/Word Protocol .........................................................................5-132
Process Call Protocol................................................................................5-133
Block Read/Write Protocol ........................................................................5-135
I²C Block Read .........................................................................................5-136
Slave Write Cycle Format .........................................................................5-139
Slave Write Registers ...............................................................................5-139
Command Types.......................................................................................5-140
Read Cycle Format ...................................................................................5-140
Data Values for Slave Read Registers .....................................................5-141
Featured Supported by ICH2 ....................................................................5-142
AC’97 Signals ...........................................................................................5-144
Input Slot 1 Bit Definitions.........................................................................5-149
Output Tag Slot 0......................................................................................5-150
AC-link state during PCIRST# ..................................................................5-153
PCI Devices and Functions...........................................................................6-2
Fixed I/O Ranges Decoded by ICH2.............................................................6-3
Variable I/O Decode Ranges ........................................................................6-5
Memory Decode Ranges from Processor Perspective .................................6-6
PCI Configuration Map (LAN Controller—B1:D8:F0)....................................7-1
Configuration of Subsystem ID and Subsystem Vendor ID via
EEPROM ......................................................................................................7-6
Data Register Structure ..............................................................................7-10
ICH2 Integrated LAN Controller CSR Space ..............................................7-10
Self-Test Results Format ............................................................................7-15
Statistical Counters .....................................................................................7-20
PCI Configuration Map (HUB-PCI—D30:F0) ................................................8-1
PCI Configuration Map (LPC I/F—D31:F0)...................................................9-1
DMA Registers............................................................................................9-23
PIC Registers..............................................................................................9-33
APIC Direct Registers .................................................................................9-41
APIC Indirect Registers...............................................................................9-41
RTC I/O Registers.......................................................................................9-47
RTC (Standard) RAM Bank ........................................................................9-47
PCI Configuration Map (PM—D31:F0) .......................................................9-54
APM Register Map......................................................................................9-60
ACPI and Legacy I/O Register Map............................................................9-61
TCO I/O Register Map ................................................................................9-79
Summary of GPIO Implementation .............................................................9-85
Registers to Control GPIO ..........................................................................9-87
PCI Configuration Map (IDE—D31:F1).......................................................10-1
Bus Master IDE I/O Registers...................................................................10-11
PCI Configuration Map (USB—D31:F2/F4) ................................................11-1
USB I/O Registers.......................................................................................11-8
Run/Stop, Debug Bit Interaction SWDBG (Bit 5),
Run/Stop (Bit 0) Operation........................................................................11-10
PCI Configuration Registers (SMBUS—D31:F3)........................................12-1
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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