82801BA Datasheet, PDF (325/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
Bit
Description
7:6 Reserved
Global Status (GBL _STS)—R/WC.
1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS has
5
a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit.
0 = The SCI handler should then clear this bit by writing a 1 to the bit location.
ICH2 (82801BA):
Reserved
ICH2-M (82801BAM):
Bus Master Status (BM_STS)— R/WC.
1 = Set by the ICH2-M when a bus master requests a break from the C3 state (the bus master
break events are generated by PIRQ[x]# assertion or bus master activity by any of ICH2-M’s
internal bus masters). Bus master activity is detected by any of the PCI requests being active,
4
any internal bus master request being active, the AGPBUSY# signal being active, or activity on
either of the ICH2-M’s USB Controllers. A USB Controller is considered active if all three of the
following conditions are true
1. The controller is not in Global Suspend
2. At least one of the controller’s ports is not suspended
3. The USB RUN bit is set
Bus Master IDE Controller activity also causes BM_STS to be set. The ICH2-M’s BMIDE
Controller is considered active when the Controller’s Start bit is set.
0 = Software clears this bit by writing a 1 to the bit position.
3:1 Reserved
Timer Overflow Status (TMROF_STS)—R/WC.
1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23).
0
This will occur every 2.3435 seconds. When the TMROF_EN bit is set, then the setting of the
TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN).
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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