82801BA Datasheet, PDF (448/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Electrical Characteristics
Table 16-7. Clock Timings (Continued)
Sym
Parameter
fac97
t26
t27
t28
t29
t30
fhl
t31
t32
t33
t34
t35
AC’97 Clock (BITCLK)
Operating Frequency
Output Jitter
High time
Low time
Rise time
Fall time
Hub Interface Clock
Operating Frequency
High time
Low time
Rise time
Fall time
CLK66 leads PCICLK
Min Max Unit Notes Figure
12.288
750
32.56 48.84
32.56 48.84
2.0
6.0
2.0
6.0
ns
ns
ns 4
ns 4
66
6.0
6.0
0.25 1.2
0.25 1.2
1.0
4.5
ns
ns
ns
ns
3
16-2
16-2
16-2
16-2
16-2
16-2
16-2
16-2
NOTES:
1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle.
2. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle
conditions.
3. This specification includes pin-to-pin skew from the clock generator as well as board skew.
4. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.
5. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
16-8
82801BA ICH2 and 82801BAM ICH2-M Datasheet