82801BA Datasheet, PDF (119/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.8.5
5.8.5.1
5.8.5.2
5.8.5.3
Front-Side Interrupt Delivery
Theory of Operation
For processors that support Front-Side Bus interrupt delivery, the ICH2 has an option to let the
integrated I/O APIC behave as an I/O (x) APIC. In this case, it delivers interrupt messages to the
processor in a parallel manner, rather than using the I/O APIC serial scheme. The ICH2 is intended
to be compatible with the I/O (x) APIC specification, Revision 1.1.
This is done by the ICH2 writing (via the Hub Interface) directly to a memory location that is
snooped by the processor(s). The processor(s) snoop the cycle to know which one goes active.
The processor enables the mode by setting the I/O APIC Enable (APIC_EN) bit and by setting the
DT bit in the I/O APIC ID register.
The following sequence is used:
1. When the ICH2 detects an interrupt event (active edge for edge-triggered mode or a change for
level-triggered mode), it sets or resets the internal IRR bit associated with that interrupt.
2. Internally, the ICH2 requests to use the bus in a way the automatically flushes upstream
buffers. This can be internally implemented similar to a DMA device request.
3. The ICH2 then delivers the message by performing a write cycle to the appropriate address
with the appropriate data. The address and data formats are described below in Section 5.8.5.5.
Notes:
1. FSB Interrupt Delivery compatibility with processor clock control depends on the processor,
not the ICH2.
2. FSB Interrupt Delivery compatibility with processor clock control depends on the processor,
not the ICH2.
3. 82801BAM (ICH2-M): FSB is not recommended in a mobile environment. For ICH2-M, if
FSB Interrupt Delivery Mode is used, the system cannot support Intel^® SpeedStep^TM
technology, C2, C3, software clock throttling or hardware thermal throttling.
Edge-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt.
The “Deassert Message” is not used.
Level-Triggered Operation
In this case, the “Assert Message” is sent when there is an inactive-to-active edge on the interrupt.
If after the EOI the interrupt is still active, then another “Assert Message” is sent to indicate that the
interrupt is still active.
If the interrupt was active but goes inactive before the EOI is received, the “Deassert Message” is
sent.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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