82801BA Datasheet, PDF (95/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.5.5 DMA Byte Enable Generation
The byte enables generated by the ICH2 on I/O reads and writes must correspond to the size of the
I/O device. Table 5-13 defines the byte enables asserted for 8 and 16 bit DMA cycles.
Table 5-13. DMA I/O Cycle Width vs. BE[3:0]#
BE[3:0]#
1110b
1100b
Description
8-bit DMA I/O Cycle: Channels 0-3
16-bit DMA I/O Cycle: Channels 5-7
NOTE: For verify cycles, the value of the Byte Enables (BEs) are a “don’t care”.
5.5.6
DMA Cycle Termination
DMA cycles are terminated when a terminal count is reached in the DMA controller and the
channel is not in autoinitialize mode or when the PC/PCI device deasserts its request. The PC/PCI
device must follow explicit rules when deasserting its request or the ICH2 may not see it in time
and run an extra I/O and memory cycle.
The PC/PCI device must deassert its request 7 PCICLKs before it generates TRDY# on the I/O
read or write cycle or the ICH2 is allowed to generate another DMA cycle. For transfers to
memory, this means that the memory portion of the cycle will be run without an asserted PC/PCI
REQ#.
5.5.7
LPC DMA
DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special
encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported
on the LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16 bit channels. Channel 4
is reserved as a generic bus master request.
5.5.8
Asserting DMA Requests
Peripherals that need DMA service encode their requested channel number on the LDRQ# signal.
To simplify the protocol, each peripheral on the LPC I/F has its own dedicated LDRQ# signal (they
may not be shared between two separate peripherals). The ICH2 has two LDRQ# inputs, allowing
at least two devices to support DMA or bus mastering.
LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-11 the peripheral uses the
following serial encoding sequence:
• Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high during idle
conditions.
• The next 3 bits contain the encoded DMA channel number (MSB first).
• The next bit (ACT) indicates whether the request for the indicated DMA channel is active or
inactive. The ACT bit will be a 1 (high) to indicate if it is active and 0 (low) if it is inactive.
The case where ACT is low will be rare, and is only used to indicate that a previous request for
that channel is being abandoned.
• After the active/inactive indication, the LDRQ# signal must go high for at least 1 clock. After
that one clock, LDRQ# signal can be brought low to the next encoding sequence.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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