82801BA Datasheet, PDF (315/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.7.5
RST_CNT—Reset Control Register
I/O Address:
Default Value:
Lockable:
CF9h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:4 Reserved.
Full Reset (FULL_RST)—R/W. This bit is used to determine the states of SLP_S3# and SLP_S5#
after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PWROK going low (with
3
RSMRST# high), or after two TCO time-outs.
1 = ICH2 will drive SLP_S3# and SLP_S5# low for 3–5 seconds.
0 = ICH2 will keep SLP_S3# and SLP_S5# high.
2
Reset Processor (RST_CPU)—R/W. When this bit transitions from a 0 to a 1, it initiates a hard or
soft reset, as determined by the SYS_RST bit (bit 1 of this register).
System Reset (SYS_RST)—R/W. This bit is used to determine a hard or soft reset to the
processor.
1 = When RST_CPU bit goes from 0 to 1, the ICH2 performs a hard reset by activating PCIRST# for
1
1 millisecond. It also resets the resume well bits (except for those noted throughout the
datasheet).
0 = When RST_CPU bit goes from 0 to 1, the ICH2 performs a soft reset by activating INIT# for 16
PCI clocks.
0 Reserved.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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