82801BA Datasheet, PDF (323/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.3 Power Management I/O Registers
Table 9-10 shows the registers associated with ACPI and Legacy power management support.
These registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be
moved to any I/O location (128-byte aligned). The registers are defined to be compliant with the
ACPI 1.0 specification, and use the same bit names.
Note: All reserved bits and registers will always return 0 when read, and will have no effect when written.
Table 9-10. ACPI and Legacy I/O Register Map
PMBASE+
Offset
00–01h
02–03h
04–07h
08–0Bh
0Ch
10h–13h
14h
15h
16–19h
20h
28–29h
2A–2Bh
2C–2D
2E–2F
30–31h
34–35h
36–3Fh
40h
42h
44h
48h
4Ch–4Dh
4Eh
50h
51–5Fh
60h–7Fh
Register Name
PM1 Status
PM1 Enable
PM1 Control
PM1 Timer
Reserved
Processor Control
Level 2
ICH2 (82801BA):
Reserved
ICH2-M (82801BAM):
Level 3
Reserved
ICH2 (82801BA):
Reserved
ICH2-M (82801BAM):
PM2 Control
General Purpose Event 0 Status
General Purpose Event 0 Enables
General Purpose Event 1 Status
General Purpose Event 1 Enables
SMI# Control and Enable
SMI Status Register
Reserved
Monitor SMI Status
Reserved
Device Trap Status
Trap Enable register
Bus Address Tracker
Bus Cycle Tracker
ICH2 (82801BA):
Reserved
ICH2-M (82801BAM):
SpeedStep™ Control
Reserved
Reserved for TCO Registers
ACPI Pointer
PM1a_EVT_BLK
PM1a_EVT_BLK+2
PM1a_CNT_BLK
PMTMR_BLK
—
P_BLK
P_BLK+4
Default
0000h
0000h
00000000h
00000000h
—
00000000h
00h
Attributes
R/W
R/W
R/W
RO
—
R/W
RO
—
P_BLK+5
—
—
—
0000h
RO
—
—
—
—
—
PM2a_CNT_BLK
0000h
R/W
GPE0_BLK
0000h
R/W
GPE0_BLK+2
0000h
R/W
GPE1_BLK
0000h
R/W
GPE1_BLK+2
0000h
R/W
—
0000h
R/W
—
0000h
R/W
—
0000h
RO
—
0000h
R/W
—
—
—
—
0000h
R/W
—
0000h
R/W
—
Last Cycle
RO
—
Last Cycle
RO
—
—
—
—
00h
WO
—
—
—
—
—
—
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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