82801BA Datasheet, PDF (206/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Figure 5-21. AC’97 2.1 Controller-Codec Connection
Digital AC '97 2.1
Controller
AC '97 2.1
controller
section of the
ICH2
RESET#
SDOUT
SYNC
BIT_CLK
SDIN 0
SDIN 1
AC '97 / AC' 97 2.1 /
AMC '97 2.1
Primary
Codec
AC '97 / MC '97 2.1 /
AMC '97 2.1
Secondary
Codec
The AC-link consists of a five signal interface between the controller and codec. Table 5-89
indicates the AC-link signal pins on the ICH2 and their associated power wells.
Table 5-89. AC’97 Signals
Signal Name
AC_RESET#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
AC_SDIN 0
AC_SDIN 1
Type
Output
Output
Input
Output
Input
Input
Power Well*
Resume
Core
Core
Core
Resume
Resume
Description
Master hardware reset
48 KHz fixed rate sample sync
12.288 MHz Serial data clock
Serial output data
Serial input data
Serial input data
NOTE: Power well voltage levels are 3.3V
ICH2 core well outputs may be used as strapping options for the ICH2, sampled during system
reset. These signals may have weak pull-ups/put-downs; however, this will not interfere with link
operation. ICH2 inputs integrate weak put-downs to prevent floating traces when a secondary
codec is not attached. When the Shut Off bit in the control register is set, all buffers will be turned
off and the pins will be held in a steady state, based on these pull-ups/put-downs.
BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the necessary
clocking to support the twelve 20 bit time slots. AC-link serial data is transitioned on each rising
edge of BIT_CLK. The receiver of AC-link data samples each serial bit on the falling edge of
BIT_CLK.
Synchronization of all AC-link data transactions is signaled by the AC’97 controller via the
AC_SYNC signal, as shown in Figure 5-22. The primary codec drives the serial bit clock onto the
AC-link, which the AC’97 controller then qualifies with the AC_SYNC signal to construct data
frames. AC_SYNC, fixed at 48 KHz, is derived by dividing down BIT_CLK. AC_SYNC remains
5-144
82801BA ICH2 and 82801BAM ICH2-M Datasheet