82801BA Datasheet, PDF (96/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
If another DMA channel also needs to request a transfer, another sequence can be sent on LDRQ#.
For example, if an encoded request is sent for channel 2 and then channel 3 needs a transfer before
the cycle for channel 2 is run on the interface, the peripheral can send the encoded request for
channel 3. This allows multiple DMA agents behind an I/O device to request use of the LPC
interface and the I/O device does not need to self-arbitrate before sending the message.
Figure 5-11. DMA Request Assertion Through LDRQ#
LCLK
LDRQ#
Start
MSB
LSB
ACT
Start
5.5.9
Abandoning DMA Requests
DMA requests can be deasserted in two fashions: on error conditions by sending an LDRQ#
message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the DMA transfer.
This section describes boundary conditions where the DMA request needs to be removed prior to a
data transfer.
There may be some special cases where the peripheral desires to abandon a DMA transfer. The
most likely case of this occurring is due to a floppy disk controller that has overrun or underrun its
FIFO, or software stopping a device prematurely.
In these cases, the peripheral wishes to stop further DMA activity. It may do so by sending an
LDRQ# message with the ACT bit as 0. However, since the DMA request was seen by the ICH2,
there is no guarantee that the cycle has not been granted and will shortly run on LPC. Therefore,
peripherals must take into account that a DMA cycle may still occur. The peripheral can choose not
to respond to this cycle, in which case the host aborts it or the host can choose to complete the
cycle normally with any random data.
This method of DMA deassertion should be prevented when possible to limit boundary conditions
both on the ICH2 and the peripheral.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet