|
82801BA Datasheet, PDF (277/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile | |||
|
◁ |
LPC Interface Bridge Registers (D31:F0)
9.1.26
9.1.27
FDD/LPT_DECâLPC I/F FDD & LPT Decode Ranges
(LPC I/FâD31:F0)
Offset Address: E1h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:5 Reserved
FDD Decode RangeâR/W. Determines which range to decode for the FDD Port
4
0 = 3F0hâ3F5h, 3F7h (Primary)
1 = 370hâ2FFh (Secondary)
3:2 Reserved
LPT Decode RangeâR/W. This field determines which range to decode for the LPT Port.
00 = 378hâ37Fh and 778hâ77Fh
1:0 01 = 278hâ27Fh (port 279h is read only) and 678hâ67Fh
10 = 3BChâ3BEh and 7BChâ7BEh
11 = Reserved
SND_DECâLPC I/F Sound Decode Ranges
(LPC I/FâD31:F0)
Offset Address: E2h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:6 Reserved
MSS Decode RangeâR/W. This field determines which range to decode for the Microsoft* Sound
System (MSS).
00 = 530hâ537h
5:4 01 = 604hâ60Bh
10 = E80hâE87h
11 = F40hâF47h
MIDI Decode RangeâR/W. This bit determines which range to decode for the Midi Port.
3
0 = 330hâ331h
1 = 300hâ301h
2 Reserved
SB16 Decode RangeâR/W. This field determines which range to decode for the Sound Blaster 16
(SB16) Port.
00 = 220hâ233h
1:0 01 = 240hâ253h
10 = 260hâ273h
11 = 280hâ293h
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-15
|
▷ |