82801BA Datasheet, PDF (453/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Electrical Characteristics
Table 16-13. IOAPIC Bus Timing
Sym
t120
t121
t122
Parameter
APICCD[1:0]# Valid Delay from APICCLK Rising
APICCD[1:0]# Setup Time to APICCLK Rising
APICCD[1:0]# Hold Time from APICCLK Rising
Min Max Units Notes Fig
3.0 12.0
ns
8.5
ns
3.0
ns
16-3
16-4
16-4
Table 16-14. SMBus Timing
Sym
Parameter
Min Max Units Notes Fig
t130 Bus Tree Time Between Stop and Start Condition
4.7
us
t131
Hold Time after (repeated) Start Condition. After this
period, the first clock is generated.
4.0
us
t132 Repeated Start Condition Setup Time
4.7
us
t133 Stop Condition Setup Time
4.0
us
t134 Data Hold Time
300
ns
t135 Data Setup Time
250
ns
t136 Device Time Out
25
35
ms 1
t137 Cumulative Clock Low Extend Time (slave device)
25
ms 2
t138 Cumulative Clock Low Extend Time (master device)
10
ms 3
16-17
16-17
16-17
16-17
16-17
16-17
16-18
16-18
NOTES:
1. A device will time out when any clock low exceeds this value.
2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the
initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines
and reset itself.
3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from start-to-ack, ack-to-ack or ack-to-stop.
Table 16-15. AC’97 Timing
Sym
t140
t141
t142
Parameter
ACSDIN[0:1] Setup to Falling Edge of BITCLK
ACSDIN[0:1] Hold from Falling Edge of BITCLK
ACSYNC, ACSDOUT valid delay from rising edge of
BITCLK
Min Max Units Notes Fig
15
ns
5
ns
15
ns
16-3
82801BA ICH2 and 82801BAM ICH2-M Datasheet
16-13