82801BA Datasheet, PDF (361/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

IDE Controller Registers (D31:F1)
10.1.14
SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1)
Address Offset: 44h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Secondary Drive 1 IORDY Sample Point (SISP1)—R/W. Determines the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data
port and bit 14 of the IDE timing register for secondary is set.
7:6 ^{00 = 5 clocks}
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Secondary Drive 1 Recovery Time (SRCT1)—R/W. Determines the minimum number of PCI clocks
between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to
drive 1 data port and bit 14 of the IDE timing register for secondary is set.
5:4 ^{00 = 4 clocks}
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
Primary Drive 1 IORDY Sample Point (PISP1)—R/W. Determines the number of PCI clocks
between IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1 data port
and bit 14 of the IDE timing register for primary is set.
3:2 ^{00 = 5 clocks}
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Primary Drive 1 Recovery Time (PRCT1)—R/W. Determines the minimum number of PCI clocks
between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the access is to
drive 1 data port and bit 14 of the IDE timing register for primary is set.
1:0 ^{00 = 4 clocks}
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
82801BA ICH2 and 82801BAM ICH2-M Datasheet
10-7