82801BA Datasheet, PDF (63/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Functional Description
5
5.1
Hub Interface to PCI Bridge (D30:F0)
The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the
ICH2 implements the buffering and control logic between PCI and the hub interface. The
arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must
decode the ranges for the hub interface. All register contents will be lost when core well power is
removed.
5.1.1 PCI Bus Interface
The ICH2 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals
are 5V tolerant. The ICH2 integrates a PCI arbiter that supports up to six external PCI bus masters
in addition to the internal ICH2 requests.
Note that most transactions targeted to the ICH2 will first appear on the external PCI bus before
being claimed back by the ICH2. The exceptions are I/O cycles involving USB, IDE, and AC’97.
These transactions will complete over the hub interface without appearing on the external PCI bus.
Configuration cycles targeting USB, IDE or AC’97 will appear on the PCI bus. If the ICH2 is
programmed for positive decode, the ICH2 will claim the cycles appearing on the external PCI bus
in medium decode time. If the ICH2 is programmed for subtractive decode, the ICH2 will claim
these cycles in subtractive time. If the ICH2 is programmed for subtractive decode, these cycles
can be claimed by another positive decode agent out on PCI. This architecture enables the ability to
boot off of a PCI card that positively decodes the boot cycles. To boot off a PCI card it is necessary
to keep the ICH2 in subtractive decode mode. When booting off a PCI card, the BOOT_STS bit
(bit 2, TCO2 Status Register) will be set.
For the 82801BAM ICH2-M, devices on the ICH2-M PCI bus (other than the ICH2-M) are not
permitted to assert the PLOCK# signal.
Note: The ICH2’s AC’97, IDE, and USB Controllers can not access PCI address ranges.
Note: PCI devices that cause long latencies (numerous retries) to processor-to-PCI Locked cycles may
starve isochronous transfers between USB or AC’97 devices and memory. This will result in
overrun or underrun, causing reduced quality of the isochronous data (e.g., audio).
Note: PCI configuration write cycles, initiated by the processor, with the following characteristics will be
converted to a Special Cycle with the Shutdown message type.
• Device Number (AD[15:11]) = ‘11111’
• Function Number (AD[10:8]) = ‘111’
• Register Number (AD[7:2]) = ‘000000’
• Data = 00h
• Bus number matches secondary bus number
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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