82801BA Datasheet, PDF (331/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
Bit
Description
ICH2 (82801BA):
Reserved
ICH2-M (82801BAM):
9 _{Global Standby Timer Status (GST_STS)— R/WC.}
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware to indicate that the wake event was due to GST timeout. This bit will only be
set when the system was in the S1 state.
RI_STS—R/WC.
8 _{0 = Software clears this bit by writing a 1 to the bit position.}
1 = Set by hardware when the RI# input signal goes active.
SMBus Wake Status (SMB_WAK_STS)—R/WC. SMBus Wake Status—R/WC. The SMBus
controller can independently cause an SMI# or SCI; thus, this bit does not need to do so (unlike the
other bits in this register).
7 _{0 = Software clears this bit by writing a 1 to the bit position.}
1 = Set by hardware to indicate that the wake event was caused by the ICH2’s SMBus logic. This
bit is set by the WAKE/SMI# command type, even if the system is already awake. The SMI
handler should then clear this bit.
TCO SCI Status (TCOSCI_STS)—R/WC.
6 _{0 = Software clears this bit by writing a 1 to the bit position.}
1 = Set by hardware when the TCO logic causes an SCI.
AC97 Status (AC97_STS)—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
5 ^{1 = Set by hardware when the codecs are attempting to wake the system. The AC97_STS bit gets}
set only from the following two cases:
1. ACSDIN[1] or ACSDIN[0] is high and BITCLK is not oscillating, or
2. The GSCI bit is set (section 13.2.9, NAMBAR +30h, bit 0)
USB Controller 2 Status (USB2_STS)—R/WC.
4 ^{0 = Software clears this bit by writing a 1 to the bit position.}
1 = Set by hardware when USB Controller 2 needs to cause a wake. Wake event will be generated
if the corresponding USB2_EN bit is set.
USB Controller 1 Status (USB1_STS)—R/WC.
3 ^{0 = Software clears this bit by writing a 1 to the bit position.}
1 = Set by hardware when USB Controller 1 needs to cause a wake. Wake event will be generated
if the corresponding USB1_EN bit is set.
2 Reserved.
Thermal Interrupt Override Status (THRMOR_STS)—R/WC.
1 ^{0 = Software clears this bit by writing a 1 to the bit position.}
1 = This bit is set by hardware anytime a thermal over-ride condition occurs and starts throttling the
processor’s clock at the THRM_DTY ratio. This will not cause an SMI#, SCI, or wake event.
Thermal Interrupt Status (THRM_STS)—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
0 _{1 = Set by hardware anytime the THRM# signal is driven active as defined by the THRM_POL bit.}
Additionally, if the THRM_EN bit is set, then the setting of the THRM_STS bit will also generate
a power management event (SCI or SMI#).
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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