82801BA Datasheet, PDF (405/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

AC’97 Audio Controller Registers (D31:F5)
13.2.4
x_SR—Status Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 06h (PISR),
NABMBAR + 16h (POSR),
NABMBAR + 26h (MCSR)
0001h
No
Attribute:
R/WC, RO (Word Access only)
Size:
16 bits
Power Well: Core
This register can be accessed only as a Word (16 bits).
Bit
15:5
4
3
2
1
0
Description
Reserved.
FIFO error (FIFOE)—R/WC.
1 = FIFO error occurs.
0 = Cleared by writing a 1 to this bit position.
PISR Register: FIFO error indicates a FIFO overrun. The FIFO pointers do not increment, the
incoming data is not written into the FIFO, thus is lost.
POSR Register: FIFO error indicates a FIFO underrun. The sample transmitted in this case should
be the last valid sample.
The ICH2 will set the FIFOE bit if the under-run or overrun occurs when there are more valid buffers
to process.
Buffer Completion Interrupt Status (BCIS)—R/WC.
1 = Set by the hardware after the last sample of a buffer has been processed, AND if the Interrupt
on Completion (IOC) bit is set in the command byte of the buffer descriptor. It remains active
until cleared by software.
0 = Cleared by writing a 1 to this bit position.
Last Valid Buffer Completion Interrupt (LVBCI)—R/WC.
1 = Last valid buffer has been processed. It remains active until cleared by software. This bit
indicates the occurrence of the event signified by the last valid buffer being processed. Thus,
this is an event status bit that can be cleared by software once this event has been
recognized. This event will cause an interrupt if the enable bit in the Control Register is set.
The interrupt is cleared when the software clears this bit.
In the case of Transmits (PCM out, Modem out) this bit is set, after the last valid buffer has
been fetched (not after transmitting it). While in the case of Receives, this bit is set after the
data for the last buffer has been written to memory.
0 = Cleared by writing a 1 to this bit position.
Current Equals Last Valid (CELV)—RO.
1 = Current Index is equal to the value in the Last Valid Index Register, and the buffer pointed to by
the CIV has been processed (i.e., after the last valid buffer has been processed). This bit is
very similar to bit 2, except this bit reflects the state rather than the event. This bit reflects the
state of the controller, and remains set until the controller exits this state.
0 = Cleared by hardware when controller exists state (i.e., until a new value is written to the LVI
register.)
DMA Controller Halted (DCH)—RO.
1 = Halted. This could happen because of the Start/Stop bit being cleared, or it could happen once
the controller has processed the last valid buffer (in which case it will set bit 1 and halt).
Software can read the above 3 registers simultaneously by scheduling a single 32 bit read from
address offset 04h. Software can also read this individual register by performing a 16 bit read from
06h.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
13-11