82801BA Datasheet, PDF (340/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.3.18
BUS_ADDR_TRACK—Bus Address Tracker Register
I/O Address:
Lockable:
Power Well:
PMBASE +4Ch
No
Core
Attribute:
Size:
Usage:
RO
16-bit
Legacy Only
This register could be used by the SMI# handler to assist in determining what was the last cycle
from the processor.
9.8.3.19
Bit
Description
Corresponds to the low 16 bits of the last I/O cycle, as would be defined by the PCI AD[15:0] signals
15:0 on the PCI bus (even though it may not be a real PCI cycle). The value is latched based on SMI#
active. This functionality is useful for figuring out which I/O was last being accessed.
BUS_CYC_TRACK—Bus Cycle Tracker Register
I/O Address:
Lockable:
Power Well:
PMBASE +4Eh
No
Core
Attribute:
Size:
Usage:
RO
8-bit
Legacy Only
This register could be used by the SMM handler to assist in determining what was the last cycle
from the processor.
9.8.3.20
Bit
Description
7:4
Corresponds to the byte enables, as would be defined by the PCI C/BE# signals on the PCI bus
(even though it may not be a real PCI cycle). The value is latched based on SMI# going active.
3:0
Corresponds to the cycle type, as would be defined by the PCI C/BE# signals on the PCI bus (even
though it may not be a real PCI cycle). The value is latched based on SMI# going active.
SS_CNT— SpeedStep^™ Control Register (82801BAM ICH2-M)
I/O Address:
Default Value
Lockable:
Power Well:
PMBASE +50h
01h
No
Core
Attribute:
Size:
Usage:
R/W (special)
8-bit
ACPI/Legacy
Writes to this register initiates an Intel^® SpeedStep^™ transition, which involves a temporary
transition to a C3-like state in which the STPCLK# signal will go active. An Intel^® SpeedStep^™
transition always occur on writes to the SS_CNT register, even if the value written to SS_STATE
is the same as the previous value (after this “transition” the system would still be in the same
Intel^® SpeedStep^™ state).
Bit
Description
7:1 Reserved
SpeedStep^TM State (SS_STATE)— R/W (Special). When this bit is read, it will return the current
SpeedStep^™ state. Writes to this register will cause a change to the SpeedStep^TM state indicated
0 ^{by the value written to this bit.}
0 = High-power state.
1 = Low-power state.
9-78
82801BA ICH2 and 82801BAM ICH2-M Datasheet