82801BA Datasheet, PDF (74/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Memory Write and Invalidate
The LAN Controller has four Direct Memory Access (DMA) channels. Of these four channels (the
receive DMA channel) is used to deposit the large number of data bytes received from the link into
system memory. The receive DMA uses both the Memory Write (MW) and the Memory Write and
Invalidate (MWI) commands. To use MWI, the LAN Controller must guarantee the following:
1. Minimum transfer of one cache line
2. Active byte enable bits (or BE[3:0]# are all low) during MWI access
3. The LAN Controller may cross the cache line boundary only if it intends to transfer the next
cache line too.
To ensure the above conditions, the LAN Controller may use the MWI command only under the
following conditions:
1. The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16
DWords.
2. The accessed address is cache line aligned.
3. The LAN Controller has at least 8 or 16 DWords of data in its receive FIFO.
4. There are at least 8 or 16 DWords of data space left in the system memory buffer.
5. The MWI Enable bit in the PCI Configuration Command register, bit 4, should is set to 1.
6. The MWI Enable bit in the LAN Controller Configure command should is set to 1.
If any one of the above conditions does not hold, the LAN Controller will use the MW command.
If a MWI cycle has started and one of the conditions is no longer valid (for example, the data space
in the memory buffer is now less than CLS), then the LAN Controller terminates the MWI cycle at
the end of the cache line. The next cycle will be either a MW or MWI cycle depending on the
conditions listed above.
If the LAN Controller started a MW cycle and reached a cache line boundary, it either continues or
terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the LAN
Controller Configure command (byte 3, bit 3). If this bit is set, the LAN Controller terminates the
MW cycle and attempts to start a new cycle. The new cycle is a MWI cycle if this bit is set and all
of the above listed conditions are met. If the bit is not set, the LAN Controller continues the MW
cycle across the cache line boundary if required.
Read Align
The Read Align feature enhances the LAN Controller’s performance in cache line oriented
systems. In these particular systems, starting a PCI transaction on a non-cache line aligned address
may cause low performance.
To resolve this performance anomaly, the LAN Controller attempts to terminate transmit DMA
cycles on a cache line boundary and start the next transaction on a cache line aligned address. This
feature is enabled when the Read Align Enable bit is set in the LAN Controller Configure
command (byte 3, bit 2).
If this bit is set, the LAN Controller operates as follows:
• When the LAN Controller is almost out of resources on the transmit DMA (i.e., the transmit
FIFO is almost full), it attempts to terminate the read transaction on the nearest cache line
boundary when possible.
• When the arbitration counter’s feature is enabled (i.e., the Transmit DMA Maximum Byte
Count value is set in the Configure command), the LAN Controller switches to other pending
DMAs on cache line boundary only.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet