82801BA Datasheet, PDF (386/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

SMBus Controller Registers (D31:F3)
12.1.9
SMB_BASE—SMBus Base Address Register
(SMBUS—D31:F3)
Address Offset: 20–23h
Default Value: 00000001h
Attribute:
Size:
R/W
32-bits
Bit
Description
31:16
15:4
3:1
0
Reserved.
Base Address—R/W. Provides the 16-bit system I/O base address for the ICH2 SMB logic.
Reserved.
IO Space Indicator—RO. This read-only bit is always 1, indicating that the SMB logic is I/O
mapped.
12.1.10
SVID—Subsystem Vendor ID (SMBUS—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
2Ch–2Dh
00h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
Subsystem Vendor ID (SVID)—RO. The SVID register, in combination with the Subsystem ID
15:0
(SID) register, enables the operating system (OS) to distinguish subsystems from each other. The
value returned by reads to this register is the same as that which was written by BIOS into the
IDE_SVID register.
12.1.11
SID—Subsystem ID (SMBUS—D31:F2/F4)
Address Offset:
Default Value:
Lockable:
2Eh–2Fh
00h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
Subsystem ID (SID)—R/Write-Once. The SID register, in combination with the SVID register,
15:0 enables the operating system (OS) to distinguish subsystems from each other. The value returned
by reads to this register is the same as that which was written by BIOS into the IDE_SID register.
12.1.12
INTR_LN—Interrupt Line Register (SMBUS—D31:F3)
Address Offset: 3Ch
Default Value: 00h
Attributes:
Size:
R/W
8 bits
Bit
Description
7:0
Interrupt line—R/W. This data is not used by the ICH2. It is to communicate to software the interrupt
line that the interrupt pin is connected to PIRQB#.
12-4
82801BA ICH2 and 82801BAM ICH2-M Datasheet