82801BA Datasheet, PDF (319/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.1.3
GEN_PMCON_3—General PM Configuration 3 Register (PM—D31:F0)
Offset Address: A4h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W
8-bit
ACPI, Legacy
RTC
9.8.1.4
Bit
Description
7:3 Reserved.
RTC Power Status (RTC_PWR_STS)—R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Indicates that the RTC battery was removed or failed. This bit is set when RTCRST# signal is
2
low.
Note: Clearing CMOS in an ICH-based platform can be done by using a jumper on RTCRST# or
GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using
a jumper to pull VccRTC low.
Power Failure (PWR_FLR)—R/WC. This bit is in the RTC well and is not cleared by any type of
reset except RTCRST#.
0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software
1
clears this bit by writing a 1 to the bit position.
1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed.
Note: Clearing CMOS in an ICH-based platform can be done by using a jumper on RTCRST# or
GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using
a jumper to pull VccRTC low.
After G3 State Select (AFTERG3_EN)—R/W. Determines what state to go to when power is re-
applied after a power failure (G3 state). This bit is in the RTC well and is not cleared by any type of
reset except writes to CF9h or RTCRST#.
0 _{0 = System will return to S0 state (boot) after power is re-applied.}
1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the
S5 state, the only enabled wake event is the Power Button or any enabled wake event that was
preserved through the power failure.
GPI_ROUT—GPI Routing Control Register (PM—D31:F0)
Offset Address:
Default Value:
Lockable:
B8h–BBh
0000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
Resume
Bit
31:30
5:4
3:2
1:0
Description
GPI[15] Route—R/W. See bits 1:0 for description.
Same pattern for GPI[14] through GPI[3]
GPI[2] Route—R/W. See bits 1:0 for description.
GPI[1] Route—R/W. See bits 1:0 for description.
GPI[0] Route—R/W. GPIO[13:11,8:6,4:3,1:0] can be routed to cause an SMI or SCI when the
GPI[n]_STS bit is set. If the GPIO is not set to an input, this field has no effect.
If the system is in an S1–S5 state and if the GPE1_EN bit is also set, then the GPI can cause a
Wake event, even if the GPI is NOT routed to cause an SMI# or SCI.
00 = No effect.
01 = SMI# (if corresponding GPE1_EN bit is also set)
10 = SCI (if corresponding GPE1_EN bit is also set)
11 = Reserved
Note: GPIOs that are not implemented will not have the corresponding bits implemented in this register.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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