82801BA Datasheet, PDF (139/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.12.5 Dynamic Processor Clock Control
ICH2 has extensive control for dynamically starting and stopping system clocks. The clock control
is used for transitions among the various S0/Cx states and processor throttling. Each dynamic clock
control method is described in this section. The various Sleep states may also perform types of non-
dynamic clock control.
The ICH2 supports the ACPI C0, C1 and C2 states.
In addition to C0, C1, and C2 states, the 82801BAM ICH2-M supports the ACPI C3 states.
The dynamic processor clock control is handled using the following signals:
• STPCLK#: Used to halt processor instruction stream.
• C3_STAT# (ICH2-M only): Used to signal an AGP device that the system is about to enter, or
has just exited a C3 state.
• STP_CPU# (ICH2-M only): Used to stop CPU’s clock
• CPUSLP#: Must be asserted prior to STP_CPU# (in Stop Grant mode)
The C1 state is entered based on the processor performing an autohalt instruction. The C2 state is
entered based on the processor reading the Level 2 register in the ICH2.
For the ICH2-M, the C3 state is entered based on the processor reading the Level 3 register in the
ICH2-M. Note that a Intel^® SpeedStep^TM transition may appear to temporarily pass through a C3
state; however, it is a separate transition and documented separately in ??.
A C1 or C2 state (C1, C2, or C3 state for the 82801BAM ICH2-M) ends due to a break event.
Based on the break event, the ICH2-M returns the system to C0 state. Table 5-40 lists the possible
break events from C2 (C2 or C3 for the ICH2-M). The break events from C1 are indicated in the
processor’s datasheet.
Table 5-40. Break Events
Event
Any unmasked interrupt goes
active
Any internal event that will
cause an NMI or SMI#
Any internal event that will
cause INIT# to go active
Any bus master request
(internal, external or DMA)
goes active
Breaks from
Comment
C2 (ICH2)
IRQ[0:15] when using the 8259s, IRQ[0:23] for I/O APIC.
Since SCI is an interrupt, any SCI will also be a break
C2, C2 (ICH2-M) _event.
C2 (ICH2)
Many possible sources
C2, C3 (ICH2-M)
C2 (ICH2)
Could be indicated by the keyboard controller via the
C2, C3 (ICH2-M) ^{RCIN input signal.}
C3 only
(ICH2-M only)
Need to wake up processor so it can do snoops
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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