82801BA Datasheet, PDF (157/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.13 System Management (D31:F0)
The ICH2 provides various functions to make a system easier to manage and to lower the Total
Cost of Ownership (TCO) of the system. Features and functions can be augmented via external
A/D converters and GPIO, as well as an external microcontroller. The following features and
functions are supported by the ICH2:
• Processor present detection.
— Detects if processor fails to fetch the first instruction after reset.
• Various Error detection (e.g., ECC Errors) indicated by Host Controller
— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
• Intruder Detect input
— Can generate TCO interrupt or SMI# when the system cover is removed.
— INTRUDER# allowed to go active in any power state, including G3.
• Detection of bad FWH programming
— Detects if data on first read is FFh (indicates unprogrammed FWH)
Note: Voltage ID from the processor can be read via GPI signals.
5.13.1
Theory of Operation
The System Management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that some of the system management functionality be
provided without the aid of an external microcontroller.
Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch
the first instruction after reset, the TCO timer times out twice and the ICH2 asserts PCIRST#.
Handling an Intruder
The ICH2 has an input signal (INTRUDER#) that can be attached to a switch that is activated by
the system’s case being open. This input has a 2 RTC clock debounce. If INTRUDER# goes active
(after the debouncer), this will set the INTRD_DET bit in the TCO_STS register. The INTRD_SEL
bits in the TCO_CNT register can enable the ICH2 to cause an SMI# or interrupt. The BIOS or
interrupt handler can then cause a transition to the S5 state by writing to the SLP_EN bit.
The software can also directly read the status of the INTRUDER# signal (high or low) by clearing
and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder
function is not required.
Note:
The INTRD_DET bit resides in the ICH2’s RTC well, and is set and cleared synchronously with
the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a “1” to the bit
location) there may be as much as 2 RTC clocks (about 65 µs) delay before the bit is actually
cleared. Also, the INTRUDER# signal should be asserted for a minimum of 1 ms to guarantee that
the INTRD_DET bit will be set.
Note:
If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET bit, the
bit will remain set and the SMI will be generated again immediately. The SMI handler can clear the
INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal goes inactive and
then active again, there will not be further SMIs, since the INTRD_SEL bits would select that no
SMI# be generated.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
5-95