82801BA Datasheet, PDF (145/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
Table 5-44. Sleep State Exit Latencies
State
S1
S3
S4
S5
Latency
<1 ms. Based on wake event to STPCLK# high + re-enumeration of PCI bus, USB, CardBus,
etc. Must also add PLL spin-up times.
Power Supply ramp + 20 ms
Power Supply ramp + 20 ms
Power Supply ramp + 20 ms
5.12.7.3 Sx–G3–Sx, Handling Power Failures
82801BAM ICH2-M: A power failure in a mobile system is a rare event, since the power
subsystem should provide sufficient warning when the batteries are low. However, if the user
removes the battery or leaves the system in an STR state for too long, a power failure could occur.
82801BA ICH2: In desktop systems, power failures can occur if the AC power is cut (a real power
failure) or if the system is unplugged. In either case, PWROK and RSMRST# are assumed to go
low.
Depending on when the power failure occurs and how the system is designed, different transitions
can occur due to a power failure.
The AFTER_G3 bit provides the ability to program whether or not the system should boot once
power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state
(unless previously in S4). There are only three possible events that will wake the system after a
power failure.
• PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low (G3
state), the PWRBTN_STS bit is reset. When the ICH2 exits G3 after power returns
(RSMRST# goes high), the PWRBTN# signal is already high (because Vcc-standby goes high
before RSMRST# goes high) and the PWRBTN_STS bit is 0.
• RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a wake event,
it is important to keep this signal powered during the power loss event. If this signal goes low
(active), when power returns, the RI_STS bit is set and the system interprets this as a wake
event.
• RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like
PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
The ICH2 monitors both PWROK and RSMRST# to detect power failures. If PWROK goes low,
the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss.
PME_EN and PME_STS bits are cleared by RSMRST#
Table 5-45. Transitions Due To Power Failure
State at Power Failure
S0, S1, S3
S4
S5
AFTERG3_EN bit
1
0
1
0
1
0
Transition When Power Returns
S5
S0
S4
S0
S5
S0
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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