82801BA Datasheet, PDF (324/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.8.3.1 PM1_STS—Power Management 1 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 00h
(ACPI PM1a_EVT_BLK)
0000h
No
Bits 0–7: Core,
Bits 8–15: Resume,
except Bit 11 in RTC
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI or Legacy
If bit 10 or 8 in this register is 1 and the corresponding _EN bit is set in the PM1_EN register, ICH2
generates a Wake Event. Once back in an S0 state (or if already in S0 state when the event occurs),
ICH2 also generates an SCI if the SCI_EN bit is set or an SMI# if the SCI_EN bit is not set.
Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but can cause an
SMI# or SCI.
Bit
Description
15
14:12
11
10
9
8
Wake Status (WAK_STS)—R/WC. This bit is not affected by hard resets caused by a CF9 write but
is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN bit) and an
enabled wake event occurs. Upon setting this bit, the ICH2 will transition the system to the ON
state.
If the AFTERG3_EN bit is not set and a power failure occurs without the SLP_EN bit set, the system
will return to an S0 state when power returns, and the WAK_STS bit will not be set. For the
82801BAM ICH2-M, power failure could result from removing the batteries.
If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having been set,
the system will go into an S5 state when power returns and a subsequent wake event will cause the
WAK_STS bit to be set. Note that any subsequent wake event would have to be caused by either a
Power Button press or an enabled wake event that was preserved through the power failure (enable
bit in the RTC well).
Reserved
Power Button Override Status (PRBTNOR_STS)—R/WC. This bit is not affected by hard resets
caused by a CF9 write and is not reset by RSMRST#. Thus, this bit will be preserved through a
power failure.
0 = The BIOS or SCI handler can clear this bit by writing a 1 to it.
1 = Set by hardware anytime a Power Button Override Event occurs which occurs when the power
button is pressed for at least 4 consecutive seconds. The power button override causes an
unconditional transition to the S5 state and sets the AFTERG3 bit. This bit can also be set by
the SMBus Slave logic.
RTC Status (RTC_STS)—R/WC. This bit is not affected by hard resets caused by a CF9 write but is
reset by RSMRST#.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal).
Additionally if the RTC_EN bit is set, the setting of the RTC_STS bit will generate a wake event.
Reserved
Power Button Status (PWRBTN_STS)—R/WC. This bit is not affected by hard resets caused by a
CF9 write.
1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any
other enable bit.
In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if
SCI_EN is not set) will be generated.
In any sleeping state S1–S5, while PWRBTN_EN and PWRBTN_STS are both set, a wake
event is generated.
0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the
PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state
with only PWRBTN# enabled as a wake event.
This bit can be cleared by software by writing a one to the bit position.
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82801BA ICH2 and 82801BAM ICH2-M Datasheet