82801BA Datasheet, PDF (199/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.17.2
5.17.3
Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low
to signal a start condition. The ICH2 continuously monitors the SMBDATA line. When the ICH2 is
attempting to drive the bus to a 1 by letting go of the SMBDATA line and it samples SMBDATA
low, then some other master is driving the bus and the ICH2 stops transferring data.
If the ICH2 sees that it has lost arbitration, the condition is called a collision. The ICH2 sets the
BUS_ERR bit in the Host Status Register, and, if enabled, generates an interrupt or SMI#. The
processor is responsible for restarting the transaction.
When the ICH2 is a SMBus master, it drives the clock. When the ICH2 is sending address or
command as an SMBus master or data bytes as a master on writes, it drives data relative to the
clock it is also driving. It does not start toggling the clock until the start or stop condition meets
proper setup and hold time. The ICH2 also guarantees minimum time between SMBus transactions
as a master.
The ICH2 supports the same arbitration protocol for both the SMBus and the System Management
(SMLINK) interfaces.
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the ICH2, as an SMBus
master, would like. They have the capability of stretching the low time of the clock. When the
ICH2 attempts to release the clock (allowing the clock to go high), the clock will remain low for an
extended period of time.
The ICH2 monitors the SMBus clock line after it releases the bus to determine whether to enable
the counter for the high time of the clock. While the bus is still low, the high time counter must not
be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if it is not
ready to send or receive data.
The ICH2 SMBus Host Controller will never stretch the low period of the clock (SMBCLK). It
always has the data to transfer on writes and it always has a spot for the data on reads.
The SMLINK interface, however, always stretches the low period of the clock, effectively forcing
transfers down to 16 KHz.
Bus Time Out (ICH2 as SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an acknowledge or
holds the clock lower than the allowed time-out time, the transaction times out. The ICH2 discards
the cycle and sets the DEV_ERR bit. The time-out minimum is 25 ms. The time-out counter inside
the ICH2 starts after the last bit of data is transferred by the ICH2 and it is waiting for a response.
The 25 ms is a count of 800 RTC clocks.
Interrupts / SMI#
The ICH2 SMBus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN
bit.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
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