82801BA Datasheet, PDF (149/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

Functional Description
5.12.9.3
Voltage Regulator Interface (82801BAM ICH2-M)
The voltage regulator interface is critical to the Intel^® SpeedStep^™ technology concept. The
power dissipation of the processor is proportional to the internal clock speed and to the square of
the core supply voltage. As the internal clock speed of the processor changes, the minimum
required core voltage supply level also changes. The interface signals are designed to allow the
voltage regulator to change settings without causing a power-on reset.
• VRCODE[4:0] is a 5-bit input to the Voltage Regulator. These signals are not outputs from
the ICH2-M; instead, they are outputs from an external muliplexer. Future voltage regulators
may integrate this multiplexer.
• The SSMUXSEL# signal is an ICH2-M output. It can be used directly to control the external
muliplexer that selects the high or low values for VRCODE[4:0].
• VRON (aka PWROK from main power supply) is an input to the regulator. When VRON is
asserted, the regulator turns on and settles to the output defined by VRCODE[4:0].
VGATE is an input from the regulator indicating that all of the outputs from the regulator are on
and within specification. When the system is transitioning between performance states, the voltage
regulator output may be required to change. It is not desirable, however, that CPUPWRGOOD
becomes deasserted during these transitions. Normally, this would indicate to the system that a
power-on reset be performed, which would invalidate the system context. The ICH2-M prevents
this from occurring by maintaining CPUPWRGOOD during the transition. CPUPWRGOOD must
also be maintained during an S1 state.
5.12.10 Event Input Signals and Their Usage
The ICH2 has various input signals that trigger specific events. This section describes those signals
and how they should be used.
5.12.10.1 PWRBTN# — Power Button
The ICH2 PWRBTN# signal operates as a “Fixed Power Button” as described in the ACPI
specification. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition
descriptions are included in the following table. Note that the transitions start as soon as the
PWRBTN# is pressed (but after the debounce logic), and does not depend on when the Power
Button is released.
Table 5-46. Transitions Due to Power Button
Present
State
S0/Cx
S1–S5
G3
S0–S4
Event
Transition/Action
Comment
PWRBTN# goes low
PWRBTN# goes low
PWRBTN# pressed
PWRBTN# held low for
at least 4 consecutive
seconds
SMI# or SCI generated
(depending on SCI_EN)
Wake Event. Transitions to S0
state.
None
Unconditional transition to S5
state.
Software will typically initiate a
Sleep state.
Standard wakeup
No effect since no power.
Not latched nor detected.
No dependence on processor
(such as Stop-Grant cycles) or
any other subsystem.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
5-87