82801BA Datasheet, PDF (351/498 Pages) Intel Corporation – Intel 82801BA I/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile

LPC Interface Bridge Registers (D31:F0)
9.10.4
GP_LVL—GPIO Level for Input or Output Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +0Ch
1B3F 0000h
No
Attribute:
Size:
Power Well:
R/W, RO
32-bit
See bit descriptions
Bit
Description
31:29, 26, 15:14,
10:9, 5, 2
(ICH2)
31:29, 26, 24:22,
20:18, 15:14, 10:9 6,
5, 2
(ICH2-M)
Reserved.
28:27, 25:24
(ICH2)
28:27, 25
(ICH2-M)
GPIO Level (GP_LVL[n])—R/W. If GPIO[n] is programmed to be an output (via the
corresponding bit in the GP_IO_SEL register), then the bit can be updated by software
to drive a high or low value on the output pin. If GPIO[n] is programmed as an input,
then software can read the bit to determine the level on the corresponding input pin.
These bits correspond to GPIO that are in the Resume well, and will be reset to their
default values by RSMRST# but not by PCIRST#.
0 = Low
1 = High
23:16
(ICH2)
21, 17:16
(ICH2-M)
GPIO Level (GP_LVL[n])—R/W. These bits can be updated by software to drive a
high or low value on the output pin. These bits correspond to GPIO that are in the
Core well, and will be reset to their default values by PCIRST#.
0 = Low
1 = High
13:11, 8:6, 4:3, 1:0
(ICH2)
13:11, 8:7, 4:3, 1:0
(ICH2-M)
ICH2 82801BA:
For GPI[13:11] and [8:6,4:3,1:0], the active status of a GPI is read from the
corresponding bit in GPE1_STS register.
ICH2-M 82801BAM:
For GPI[13:11] and [8:7,4:3,1:0], the active status of a GPI is read from the
corresponding bit in GPE1_STS register.
82801BA ICH2 and 82801BAM ICH2-M Datasheet
9-89